Derive the Boolean expression for the gate structure that clears the sequence counter SC to 0. Draw the logic diagram of the gates and show how the output is connected to the lNR and CLR inputs of SC (see Fig. 5-6). Minimize the number of gates.
Derive the Boolean expression for the gate structure that clears the sequence counter SC to 0. Draw the logic diagram of the gates and show how the output is connected to the lNR and CLR inputs of SC (see Fig. 5-6). Minimize the number of gates.
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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- Derive the Boolean expression for the gate structure that clears the sequence counter SC to 0. Draw the logic diagram of the gates and show how the output is connected to the lNR and CLR inputs of SC (see Fig. 5-6). Minimize the number of gates.
![TABLE 5-6 Control Functions and Microoperations for the Basic Computer
R'T:
R'T;:
R'T:
Fetch
AR + PC
IR M[AR), PC+PC + 1
Do, ..., D,+Decode IR(12-14),
AR +IR(0-11), I+IR(15)
AR +M[AR]
Decode
Indirect
D:IT;
Interrupt:
TTT:(IENXFGI + FGO):
RT::
RT;:
RT:
R+1
AR +0, TR+PC
M[AR]+TR, PC+0
РC+ РC + 1, IEN-0, R+0, SC-0
Memory-reference:
AND
DR +M[AR]
D.T3:
D,T:
DiTs:
DT:
D:Ts:
AC+AC A DR, SC+0
DR +M[AR]
AC+AC + DR, E+Cou SC+0
DR +M[AR]
AC+DR, SC -0
M[AR]+AC, SC+0
PC+AR, SC+0
ADD
LDA
D,T:
D.T:
STA
BUN
M[AR]+PC, AR+AR + 1
PC +AR, SC+0
DR +M[AR]
BSA
D,T;:
ISZ
D.T:
D.T;:
D.T:
DR+DR + 1
M[AR] –DR, if(DR = 0) then (PC +PC + 1), sC-0
Register-reference:
D,I'T, = r (common to all register-reference instructions)
IR(i) = B, (i = 0, 1, 2, . , 11)
r:
SC+0
CLA
rBu:
rB10:
rB:
AC+0
CLE
СМА
СМЕ
CIR
E+0
AC -AC
rB:
rB:
AC-shr AC, AC(15) - Е, Е-AC (0)
АС+shl AC, AC(0)-Е, Е-AC(15)
CIL
INC
rB:
rBs
rB:
AC+AC + 1
и (АC(15) - 0) then (PC +- PC + 1)
If (AC(15) = 1) then (PC+PC + 1)
If (AC = 0) then PC+PC + 1)
If (E = 0) then (PC -PC + 1)
SPA
SNA
rBy
rB:
rB:
rBo
SZA
SZE
HLT
S+0
Input-output:
D;IT, = p (common to all input-output instructions)
IR(i) = B. (i = 6, 7, 8, 9, 10, 11)
p:
SC+0
pBu: AC(0-7)INPR, FGI +0
pBie:
INP
OUTRAC(0-7), FGO+0
If (FGI = 1) then (PC +PC + 1)
If (FGO = 1) then (PC +PC + 1)
IEN+1
OUT
SKI
SKO
ION
pBy:
pB:
IOF
IEN+0](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Fc353cc0f-0c4d-4d5b-a3e6-e746dbb90f94%2F7296fe20-f894-4e9a-8654-5d1569edce41%2Fwkrda3l_processed.png&w=3840&q=75)
Transcribed Image Text:TABLE 5-6 Control Functions and Microoperations for the Basic Computer
R'T:
R'T;:
R'T:
Fetch
AR + PC
IR M[AR), PC+PC + 1
Do, ..., D,+Decode IR(12-14),
AR +IR(0-11), I+IR(15)
AR +M[AR]
Decode
Indirect
D:IT;
Interrupt:
TTT:(IENXFGI + FGO):
RT::
RT;:
RT:
R+1
AR +0, TR+PC
M[AR]+TR, PC+0
РC+ РC + 1, IEN-0, R+0, SC-0
Memory-reference:
AND
DR +M[AR]
D.T3:
D,T:
DiTs:
DT:
D:Ts:
AC+AC A DR, SC+0
DR +M[AR]
AC+AC + DR, E+Cou SC+0
DR +M[AR]
AC+DR, SC -0
M[AR]+AC, SC+0
PC+AR, SC+0
ADD
LDA
D,T:
D.T:
STA
BUN
M[AR]+PC, AR+AR + 1
PC +AR, SC+0
DR +M[AR]
BSA
D,T;:
ISZ
D.T:
D.T;:
D.T:
DR+DR + 1
M[AR] –DR, if(DR = 0) then (PC +PC + 1), sC-0
Register-reference:
D,I'T, = r (common to all register-reference instructions)
IR(i) = B, (i = 0, 1, 2, . , 11)
r:
SC+0
CLA
rBu:
rB10:
rB:
AC+0
CLE
СМА
СМЕ
CIR
E+0
AC -AC
rB:
rB:
AC-shr AC, AC(15) - Е, Е-AC (0)
АС+shl AC, AC(0)-Е, Е-AC(15)
CIL
INC
rB:
rBs
rB:
AC+AC + 1
и (АC(15) - 0) then (PC +- PC + 1)
If (AC(15) = 1) then (PC+PC + 1)
If (AC = 0) then PC+PC + 1)
If (E = 0) then (PC -PC + 1)
SPA
SNA
rBy
rB:
rB:
rBo
SZA
SZE
HLT
S+0
Input-output:
D;IT, = p (common to all input-output instructions)
IR(i) = B. (i = 6, 7, 8, 9, 10, 11)
p:
SC+0
pBu: AC(0-7)INPR, FGI +0
pBie:
INP
OUTRAC(0-7), FGO+0
If (FGI = 1) then (PC +PC + 1)
If (FGO = 1) then (PC +PC + 1)
IEN+1
OUT
SKI
SKO
ION
pBy:
pB:
IOF
IEN+0
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