Hardware & Architecture HW #5 - 100 Pts 6. a. (8 Pts) Label the Boolean output of each gate. Note: The labels you need are giving in the Table for Part b; you only need to map each to the correct location in the circuit. b. Using the table provided, derive a Truth Table for the Output B Inputs (3 Pts) D 3 Pts 2 Pts 3 Pts 3 Pts 2 Pts 3 Pts. A B C D A A+B T BC 3 Pts C+D A+ B+ BC (A + B)(C + D) 0 0 0 0 00 0 1 0 0 1 0 0 0 1 1 O 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 00 0 1 0 0 1 1 0 1 0 0 1 1 1 1 00 1 0 1 1 1 1 0 1 1 1 3 Pts A+B+BC+(A + B) (C + D)

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Hardware & Architecture HW #5 - 100 Pts
6.
a. (8 Pts) Label the Boolean output of each gate. Note: The
labels you need are giving in the Table for Part b; you only
need to map each to the correct location in the circuit.
b. Using the table provided, derive a Truth Table for the Output
B
Inputs (3 Pts)
D
3 Pts
2 Pts 3 Pts
3 Pts
2 Pts
3 Pts.
A
B C D
A A+B
T
BC
3 Pts
C+D
A+ B+ BC
(A + B)(C + D)
0 0 0 0
00 0
1
0 0 1
0
0
0
1
1
O
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
00
0
1
0
0
1
1
0
1
0
0
1
1
1
1
00
1
0
1
1
1
1
0
1
1
1
3 Pts
A+B+BC+(A + B) (C + D)
Transcribed Image Text:Hardware & Architecture HW #5 - 100 Pts 6. a. (8 Pts) Label the Boolean output of each gate. Note: The labels you need are giving in the Table for Part b; you only need to map each to the correct location in the circuit. b. Using the table provided, derive a Truth Table for the Output B Inputs (3 Pts) D 3 Pts 2 Pts 3 Pts 3 Pts 2 Pts 3 Pts. A B C D A A+B T BC 3 Pts C+D A+ B+ BC (A + B)(C + D) 0 0 0 0 00 0 1 0 0 1 0 0 0 1 1 O 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 00 0 1 0 0 1 1 0 1 0 0 1 1 1 1 00 1 0 1 1 1 1 0 1 1 1 3 Pts A+B+BC+(A + B) (C + D)
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