1. Consider the following design requirement: A majority logic is a digital circuit whose output is equal to 1 if the majority of the inputs are 1s. The output is 0 otherwise. Design and test a 3-input majority circuit using NAND gates with minimum number of ICs. 2. Obtain the truth table (Table 7-19) of the circuit.
1. Consider the following design requirement: A majority logic is a digital circuit whose output is equal to 1 if the majority of the inputs are 1s. The output is 0 otherwise. Design and test a 3-input majority circuit using NAND gates with minimum number of ICs. 2. Obtain the truth table (Table 7-19) of the circuit.
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
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1

Transcribed Image Text:1. Consider the following design requirement:
A majority logic is a digital circuit whose output is equal to 1 if the
majority of the inputs are 1s. The output is 0 otherwise. Design and
test a 3-input majority circuit using NAND gates with minimum
number of ICs.
2. Obtain the truth table (Table 7-19) of the circuit.
Input
Output
B
Y
0
0
1
1
0
0
1
1
TABLE 7-19. Truth Table
A
oooo
0
0
0
0
1
1
1
1
C
0
1
0
1
0
1
0
1

Transcribed Image Text:Simplify the equation No
MENT DECODER
= Y
udent must be able to
Draw the logic diagram (Figure 7-16) of the circuit using NAND gates
and with a minimum number of ICs.
of the
quired:
Entegrated Circuits
47 BCD-to-seven Segment Decoder
Supply (5V-9V)
-segment display
0,0.5 watt, 5% resistors
ecting wires (solid)
strippers/cutter
SEGMENT DISPLAY FIGURE 7-16. Logic Diagram
Construct the circuit using TTL NAND gates.
Test the circuit for proper operation by verifying the truth table,
Table 7-19.
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