Integer Instruction gap gcc gzip mcf perlbmk average load 26.5% 25.1% 20.1% 30.3% 28.7% 26% store 10.3% 13.2% 5.1% 4.3% 16.2% 10% add 21.1% 19.0% 26.9% 10.1% 16.7% 19% sub 1.7% 2.2% 5.1% 3.7% 2.5% 3% mul 1.4% 0.1% 0% compare 2.8% 6.1% 6.6% 6.3% 3.8% 5% load imm 4.8% 2.5% 1.5% 0.1% 1.7% 2% cond branch 9.3% 12.1% 11.0% 17.5% 10.9% 12% cond move 0.4% 0.6% 1.1% 0.1% 1.9% 1% jump 0.8% 0.7% 0.8% 0.7% 1.7% 1% call 1.6% 0.6% 0.4% 3.2% 1.1% 1% return 1.6% 0.6% 0.4% 3.2% 1.1% 1% shift 3.8% 1.1% 2.1% 1.1% 0.5% 2% AND 4.3% 4.6% 9.4% 0.2% 1.2% 4% OR 7.9% 8.5% 4.8% 17.6% 8.7% 9% XOR 1.8% 2.1% 4.4% 1.5% 2.8% 3% other logical 0.1% 0.4% 0.1% 0.1% 0.3% 0% load FP 0% store FP 0% add FP 0% sub FP 0% mul FP 0% div FP mov reg-reg FP compare FP cond mov FP 0% 0% 0% 0% other FP 0% Figure A.27 MIPS dynamic instruction mix for five SPECint2000 programs. Note that integer register-register move instructions are included in the OR instruction. Blank entries have the value 0.0%. A.20 [20/20/20] We are designing instruction set formats for a load-store archi- tecture and are trying to decide whether it is worthwhile to have multiple offset lengths for branches and memory references. The length of an instruction would be equal to 16 bits + offset length in bits, so ALU instructions will be 16 bits. Figure A.31 contains data on offset size for the Alpha architecture with full opti- mization for SPEC CPU2000. For instruction set frequencies, use the data for MIPS from the average of the five benchmarks for the load-store machine in Fig- ure A.27. Assume that the miscellaneous instructions are all ALU instructions that use only registers. Exercises by Gregory D. Peterson A-53 Number of offset magnitude bits 0 1 Cumulative data references Cumulative branches 30.4% 0.1% 33.5% 2.8% 2 35.0% 10.5% 3 40.0% 22.9% 4 47.3% 36.5% 5 54.5% 57.4% 6 60.4% 72.4% 7 66.9% 85.2% 8 71.6% 90.5% 9 73.3% 93.1% 10 74.2% 95.1% 11 74.9% 96.0% 12 76.6% 96.8% 13 87.9% 97.4% 14 91.9% 98.1% 15 100% 98.5% 16 100% 99.5% 17 100% 99.8% 18 100% 99.9% 19 100% 100% 20 100% 100% 21 100% 100% Figure A.31 Data on offset size for the Alpha architecture with full optimization for SPEC CPU2000. a. [20] Suppose offsets are permitted to be 0, 8, 16, or 24 bits in length, including the sign bit. What is the average length of an executed instruction?
Integer Instruction gap gcc gzip mcf perlbmk average load 26.5% 25.1% 20.1% 30.3% 28.7% 26% store 10.3% 13.2% 5.1% 4.3% 16.2% 10% add 21.1% 19.0% 26.9% 10.1% 16.7% 19% sub 1.7% 2.2% 5.1% 3.7% 2.5% 3% mul 1.4% 0.1% 0% compare 2.8% 6.1% 6.6% 6.3% 3.8% 5% load imm 4.8% 2.5% 1.5% 0.1% 1.7% 2% cond branch 9.3% 12.1% 11.0% 17.5% 10.9% 12% cond move 0.4% 0.6% 1.1% 0.1% 1.9% 1% jump 0.8% 0.7% 0.8% 0.7% 1.7% 1% call 1.6% 0.6% 0.4% 3.2% 1.1% 1% return 1.6% 0.6% 0.4% 3.2% 1.1% 1% shift 3.8% 1.1% 2.1% 1.1% 0.5% 2% AND 4.3% 4.6% 9.4% 0.2% 1.2% 4% OR 7.9% 8.5% 4.8% 17.6% 8.7% 9% XOR 1.8% 2.1% 4.4% 1.5% 2.8% 3% other logical 0.1% 0.4% 0.1% 0.1% 0.3% 0% load FP 0% store FP 0% add FP 0% sub FP 0% mul FP 0% div FP mov reg-reg FP compare FP cond mov FP 0% 0% 0% 0% other FP 0% Figure A.27 MIPS dynamic instruction mix for five SPECint2000 programs. Note that integer register-register move instructions are included in the OR instruction. Blank entries have the value 0.0%. A.20 [20/20/20] We are designing instruction set formats for a load-store archi- tecture and are trying to decide whether it is worthwhile to have multiple offset lengths for branches and memory references. The length of an instruction would be equal to 16 bits + offset length in bits, so ALU instructions will be 16 bits. Figure A.31 contains data on offset size for the Alpha architecture with full opti- mization for SPEC CPU2000. For instruction set frequencies, use the data for MIPS from the average of the five benchmarks for the load-store machine in Fig- ure A.27. Assume that the miscellaneous instructions are all ALU instructions that use only registers. Exercises by Gregory D. Peterson A-53 Number of offset magnitude bits 0 1 Cumulative data references Cumulative branches 30.4% 0.1% 33.5% 2.8% 2 35.0% 10.5% 3 40.0% 22.9% 4 47.3% 36.5% 5 54.5% 57.4% 6 60.4% 72.4% 7 66.9% 85.2% 8 71.6% 90.5% 9 73.3% 93.1% 10 74.2% 95.1% 11 74.9% 96.0% 12 76.6% 96.8% 13 87.9% 97.4% 14 91.9% 98.1% 15 100% 98.5% 16 100% 99.5% 17 100% 99.8% 18 100% 99.9% 19 100% 100% 20 100% 100% 21 100% 100% Figure A.31 Data on offset size for the Alpha architecture with full optimization for SPEC CPU2000. a. [20] Suppose offsets are permitted to be 0, 8, 16, or 24 bits in length, including the sign bit. What is the average length of an executed instruction?
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
Related questions
Question
Transcribed Image Text:Integer
Instruction
gap
gcc
gzip
mcf
perlbmk
average
load
26.5%
25.1%
20.1%
30.3%
28.7%
26%
store
10.3%
13.2%
5.1%
4.3%
16.2%
10%
add
21.1%
19.0%
26.9%
10.1%
16.7%
19%
sub
1.7%
2.2%
5.1%
3.7%
2.5%
3%
mul
1.4%
0.1%
0%
compare
2.8%
6.1%
6.6%
6.3%
3.8%
5%
load imm
4.8%
2.5%
1.5%
0.1%
1.7%
2%
cond branch
9.3%
12.1%
11.0%
17.5%
10.9%
12%
cond move
0.4%
0.6%
1.1%
0.1%
1.9%
1%
jump
0.8%
0.7%
0.8%
0.7%
1.7%
1%
call
1.6%
0.6%
0.4%
3.2%
1.1%
1%
return
1.6%
0.6%
0.4%
3.2%
1.1%
1%
shift
3.8%
1.1%
2.1%
1.1%
0.5%
2%
AND
4.3%
4.6%
9.4%
0.2%
1.2%
4%
OR
7.9%
8.5%
4.8%
17.6%
8.7%
9%
XOR
1.8%
2.1%
4.4%
1.5%
2.8%
3%
other logical
0.1%
0.4%
0.1%
0.1%
0.3%
0%
load FP
0%
store FP
0%
add FP
0%
sub FP
0%
mul FP
0%
div FP
mov reg-reg FP
compare FP
cond mov FP
0%
0%
0%
0%
other FP
0%
Figure A.27 MIPS dynamic instruction mix for five SPECint2000 programs. Note that integer register-register
move instructions are included in the OR instruction. Blank entries have the value 0.0%.
![A.20 [20/20/20] <A.3> We are designing instruction set formats for a load-store archi-
tecture and are trying to decide whether it is worthwhile to have multiple offset
lengths for branches and memory references. The length of an instruction would
be equal to 16 bits + offset length in bits, so ALU instructions will be 16 bits.
Figure A.31 contains data on offset size for the Alpha architecture with full opti-
mization for SPEC CPU2000. For instruction set frequencies, use the data for
MIPS from the average of the five benchmarks for the load-store machine in Fig-
ure A.27. Assume that the miscellaneous instructions are all ALU instructions
that use only registers.
Exercises by Gregory D. Peterson
A-53
Number of offset
magnitude bits
0
1
Cumulative data
references
Cumulative branches
30.4%
0.1%
33.5%
2.8%
2
35.0%
10.5%
3
40.0%
22.9%
4
47.3%
36.5%
5
54.5%
57.4%
6
60.4%
72.4%
7
66.9%
85.2%
8
71.6%
90.5%
9
73.3%
93.1%
10
74.2%
95.1%
11
74.9%
96.0%
12
76.6%
96.8%
13
87.9%
97.4%
14
91.9%
98.1%
15
100%
98.5%
16
100%
99.5%
17
100%
99.8%
18
100%
99.9%
19
100%
100%
20
100%
100%
21
100%
100%
Figure A.31 Data on offset size for the Alpha architecture with full optimization for
SPEC CPU2000.
a. [20] <A.3> Suppose offsets are permitted to be 0, 8, 16, or 24 bits in length,
including the sign bit. What is the average length of an executed instruction?](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F8ba6b41e-3d5b-4a7e-98b1-cdb14c7efe09%2Fdc17ade3-df1c-45de-9288-1d6fb05e3a15%2Fzn9mrgcr_processed.png&w=3840&q=75)
Transcribed Image Text:A.20 [20/20/20] <A.3> We are designing instruction set formats for a load-store archi-
tecture and are trying to decide whether it is worthwhile to have multiple offset
lengths for branches and memory references. The length of an instruction would
be equal to 16 bits + offset length in bits, so ALU instructions will be 16 bits.
Figure A.31 contains data on offset size for the Alpha architecture with full opti-
mization for SPEC CPU2000. For instruction set frequencies, use the data for
MIPS from the average of the five benchmarks for the load-store machine in Fig-
ure A.27. Assume that the miscellaneous instructions are all ALU instructions
that use only registers.
Exercises by Gregory D. Peterson
A-53
Number of offset
magnitude bits
0
1
Cumulative data
references
Cumulative branches
30.4%
0.1%
33.5%
2.8%
2
35.0%
10.5%
3
40.0%
22.9%
4
47.3%
36.5%
5
54.5%
57.4%
6
60.4%
72.4%
7
66.9%
85.2%
8
71.6%
90.5%
9
73.3%
93.1%
10
74.2%
95.1%
11
74.9%
96.0%
12
76.6%
96.8%
13
87.9%
97.4%
14
91.9%
98.1%
15
100%
98.5%
16
100%
99.5%
17
100%
99.8%
18
100%
99.9%
19
100%
100%
20
100%
100%
21
100%
100%
Figure A.31 Data on offset size for the Alpha architecture with full optimization for
SPEC CPU2000.
a. [20] <A.3> Suppose offsets are permitted to be 0, 8, 16, or 24 bits in length,
including the sign bit. What is the average length of an executed instruction?
Expert Solution
This question has been solved!
Explore an expertly crafted, step-by-step solution for a thorough understanding of key concepts.
Step by step
Solved in 2 steps with 2 images
Recommended textbooks for you
Computer Networking: A Top-Down Approach (7th Edi…
Computer Engineering
ISBN:
9780133594140
Author:
James Kurose, Keith Ross
Publisher:
PEARSON
Computer Organization and Design MIPS Edition, Fi…
Computer Engineering
ISBN:
9780124077263
Author:
David A. Patterson, John L. Hennessy
Publisher:
Elsevier Science
Network+ Guide to Networks (MindTap Course List)
Computer Engineering
ISBN:
9781337569330
Author:
Jill West, Tamara Dean, Jean Andrews
Publisher:
Cengage Learning
Computer Networking: A Top-Down Approach (7th Edi…
Computer Engineering
ISBN:
9780133594140
Author:
James Kurose, Keith Ross
Publisher:
PEARSON
Computer Organization and Design MIPS Edition, Fi…
Computer Engineering
ISBN:
9780124077263
Author:
David A. Patterson, John L. Hennessy
Publisher:
Elsevier Science
Network+ Guide to Networks (MindTap Course List)
Computer Engineering
ISBN:
9781337569330
Author:
Jill West, Tamara Dean, Jean Andrews
Publisher:
Cengage Learning
Concepts of Database Management
Computer Engineering
ISBN:
9781337093422
Author:
Joy L. Starks, Philip J. Pratt, Mary Z. Last
Publisher:
Cengage Learning
Prelude to Programming
Computer Engineering
ISBN:
9780133750423
Author:
VENIT, Stewart
Publisher:
Pearson Education
Sc Business Data Communications and Networking, T…
Computer Engineering
ISBN:
9781119368830
Author:
FITZGERALD
Publisher:
WILEY