Question 04: For the hexadecimal main memory addresses 111111, 666666, BBBBBB, show thefollowing information, in hexadecimal format:a. Tag, Line, and Word values for a direct-mapped cache.b. Tag and Word values for an associative cache.c. Tag, Set, and Word values for a two-way set-associative cache.

To answer these, we need to make some assumptions about the cache architecture, as details like the…

Answered: Question 04: For the hexadecimal main…

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter6: System Integration And Performance

Section: Chapter Questions

Problem 22VE

See similar textbooks

Similar questions

3. The table below represents five lines from a cache that uses fully associative mapping with a block size of 8. Identify the address of the shaded data, 0xE6, first in binary and then in hexadecimal. The tag numbers and word id bits are in binary, but the content of the cache (the data) is in hexadecimal. Word id bits Tag 000 001 010 011 100 101 110 111 ------------------------------------------ 1011010 10 65 BA 0F C4 19 6E C3 1100101 21 76 CB 80 D5 2A 7F B5 0011011 32 87 DC 91 E6 3B F0 A6 1100000 43 98 ED A2 F7 4C E1 97 1111100 54 9A FE B3 08 5D D2 88
For a direct-mapped cache design with 64-bit addresses, the following bits of the address are used to access the cache: Tag Index Offset 63-13 12-4 3-0 a. What is the cache block size (in bytes)?b. What is the cache size (in bytes)?c. What is the total number of bits (including valid bit, tag bits and data array bits) to implement this cache?d. For the same block and cache sizes, you want to implement a 4-way set-associative cache, what is the number of index bit and the number of tag bits?
For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache: Tag Index Offset 31-10 9-6 5-0 1. What is the cache block size (in words)? 2. How many entries does the cache have? 3. What is the ratio between total bits required for such a cache implementation over the data storage bits?
For a direct-mapped cache design with a 32-bit address, the following bitsof the address are used to access the cache. Use the table below. a. What is the cache block size (in words)?b. How many entries does the cache have?c. What is the ration between total bits required for such a cache implementation overthe data storage bit?
What are the three fields in a set-associative cache address, and how are they used to access a location in cache?
In a microprocessor of 32 bit addresses, the tag length will change if we design a two-way set-associate cache versus a four-way set-associative cache, with the same number of cache lines in each organization, and the same number of data bytes per set. a. True b. False
For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache. Tag Index Offset 63-9 8-5 4-0 Beginning from power on, the following byte-addressed cache references are recorded. Нех 00 04 10 84 E8 AO 400 1E 8C Cic B4 884 (A) For cach reference, list (i) its teg, index, end offset, (ii) whether it is a hit or a miss, and (iii) which bytes were replaced (if any). (B) what is the hit ratio? (C) List the final state of the cache, with each valid entry represented as a record of . For example,
For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. a. What is the cache block size in words? b. How many entries does the cache have? Tag 31-13 Index 12-6 Offset 5-0
For the hexadecimal main memory addresses 111111, 666666, BBBBBB, show thefollowing information, in hexadecimal format: Tag, Line, and Word values for a direct- mapped cache, using the format of Figure b. Tag and Word values for an associative cache, using the format of Figure
For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache. Tag Index Offset 63-9 8-5 |4-0 Beginning from power on, the following byte-addressed cache references are recorded. |Нех 00 04 10 84 E8 A0 | 400||1E 8C C1C B4 884 (A) For each reference, list (i) its tag, index, and offset, (ii) whether it is a hit or a miss, and (iii) which bytes were replaced (if any). (B) What is the hit ratio? (C) List the final state of the cache, with each valid entry represented as a record of . For example,
For a direct-mapped cache design with a 32-bit address, the following bits of the address areused to access the cache.Tag Index Offset31–10 9–6 5–0a– What is the cache block size (in words)? b – How many entries does the cache have? c – What is the ratio between total bits required for such a cache implementation overthe data storage bits?
We are given a list of 64-bit memory address references, given as word addresses. Ox03, Oxb4, Ox2b, 0x02, Oxbf, Ox58, Oxbe, OxOe, Oxb5, Ox2c, Oxba, Oxfd (A) For each of these references, identify the binary word address, the tag, and the index given a direct-mapped cache with 16 one-word blocks. Also list whether each reference is a hit or a miss, assuming the cache is initially empty. (B) For each of these references, identify the binary word address, the tag, the index, and the offset given a direct-mapped cache with two- word blocks and a total size of eight blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. (C) You are asked to optimize a cache design for the given references (i.e. addresses). There are three direct-mapped cache designs possible, all with a total of eight words of data: (i) Cache1 has 1-word blocks, (ii) Cache2 has 2-word blocks, and (iii) Cache3 has 4-word blocks.

SEE MORE QUESTIONS

Recommended textbooks for you

Systems Architecture

Computer Science

ISBN:

9781305080195

Author:

Stephen D. Burd

Publisher:

Cengage Learning

Systems Architecture

Computer Science

ISBN:

9781305080195

Author:

Stephen D. Burd

Publisher:

Cengage Learning

SEE MORE TEXTBOOKS