Q:Consider computing theoverall MIPS for a machine A forwhich the followingperformance measures wererecorded when executing a setof benchmark programs.Assume that the clock rate ofthe CPU is 400 MHzInstruction categoryPercentage ofNo. of cycles peroccurrenceinstructionALU301LOAD from MemorySTORE to Memory20310Branch15Call subroutine5O MIPS=125.490MIPS=155.423O MIPS=122.374MIPS=156.102 Q:Find the cycle time CT, If theclock frequency is 4 GHZ, CT=?sec0.25nsec0.025 nseCO 0.25 u secO 0.250X10^9Q:For the following microoperation find Boolean Function *F

Average number of cycles per instruction = 30*1 + 20*3 + 10*5 + 15*7 + 5*2 / 100 = 255/100 = 2.55…

Q:Consider computing the overall MIPS for a machine A for which the following performance measures were recorded when executing a set of benchmark programs. Assume that the clock rate of the CPU is 400 MHz * No. of cycles per instruction Instruction category Percentage of осcurrence 30 ALU 1 LOAD from Memory STORE to Memory 20 10 Branch 15 7 Call subroutine 5

Q:Consider computing the overall MIPS for a machine A for which the following performance measures were recorded when executing a set of benchmark programs. Assume that the clock rate of the CPU is 400 MHz * No. of cycles per instruction Instruction category Percentage of осcurrence 30 ALU 1 LOAD from Memory STORE to Memory 20 10 Branch 15 7 Call subroutine 5

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

Let's consider Tomasulo's algorithm. Assume load takes two cycles in execute, add takes three cycles, and a multiple takes seven cycles. Schedule the following code sequence using the instruction status, reservation station, and register status tables and indicate the total number of clock cycles used to complete the code. Show the information tables when the first add has completed and written its result. F2, 0 (x1) FO, F2, F4 F6, FO, F2 T1: fid T2: fmult.d T3: fadd.d T4: fadd.d F2, F4, F2
Program X Instruction Count = 29 x 105 Program Y Instruction Count = 18 x 105 Processor 1 Clock Rate = 3.3GHZ Execution Time 12ms Execution Time 9ms Table 1.0 Processor 2 Clock Rate = 2.8GHZ Execution Time 16ms Execution Time 7ms Answer the following questions based on the information above. *You are required to indicate all working steps and marks will be given accordingly. (a) Calculate the instruction execution rate for BOTH processors when running BOTH programs.
clock cycle at which the first of the instructions is fetched as clock cycle 1. Assume that if one instruction reads a register during the same clock cycle as another instruction is writing it, the new value will be read. Do not reorder the instructions. Instructions are fetched and executed exactly in the order given below, with the pipeline stalling if necessary.addi $s2, $s2, 1li $s6, 5add $s1, $s2, $s3move $s5, $s6lw $t1, 0($s5)
Consider computing the overall CPI for a machine Z for which the following performance measures were recorded when executing a set of benchmark programs. Assume that the clock rate of the CPU is 200 MHz .find CPIZ Instruction Percentage of No. of cycles category per instruction OCcurrence ALU 25 4 LOAD&STORE 6. BRANCHES 30 OTHER 40 1
Question 2. A program is executed for 1 sec, on a processor with a clock cycle of 100 nsec and CPI₁ = 1,5. 1. How much is the Throughput, expressed in MIPS? 2. Let us assume that, given some optimization techniques, the 30% of the program instructions is executed with CPI = 1, while the fraction of remaining instructions (70%) is executed with the same CPI. a. How much is the Speedup from the case (1) to the case (2)? b. How much is the Throughput expressed in MIPS?
calculate the rate of MIPS by executing a program that has 600 MHz processor and 1 million instructions, also the CPI of each instruction type are 1,2,4,8 and the instructions are logical, load, branch, memory respectively where the instruction mix are given as 30%, 15%, 25% and 30%. Trace the result after execution.
compute MIPS for two different machines running a given set of benchmark programs: No. of No. of instructions cycles per instruction Instruction category (in millions) Machine (A) ALU 8 1 Load & store 4 3 Branch Others Machine (B) ALU 10 1 Load & store 8. 2 Branch Others 4
1
Take the accompanying project fragment for a theoretical CPU having three client registers R1, R2 and R3. Guidance Operation Instruction Size(in words) MOV R1,5000; R1- Memory[5000] MOV R2, (R1); R2 - Memory[(R1)] ADD R2, R3; MOV 6000, R2; 2 1 R2 - R2 + R3 1 Memory [6000] – R2 End Machine ends 1 Leave the clock cycles needed for different tasks alone as follows: Register to/from memory move: 3 clock cycles ADD with the two operands in register : 1 clock cycle Instruction get and unravel : 2 clock cycles for each word The absolute number of clock cycles needed to execute the program is
The subject is “information Technology”. The topic of the questions are under the little Man Computer .
A particular (fictional) CPU has the following internal units and timings (WRand RR are write/read registers,ALU does all logic and integer operations and there is a separate floatingpoint unit FPU. Timings for each unit in picoseconds are:IR 230, RR 40, WR 50, ALU 200, MEM 260, FPU 380(assume instruction read and memory access are average time for access tocache)There are 5 basic instruction types: - here are instruction sequence for eachtype, time in picoseconds and percentage of each type in a typical set of testcodes:1. LOAD : IR+RR+ALU+MEM+WR : 780, 20%2. STORE: IR+RR+ALU+MEM : 730, 10%3. LOGIC/INTEGER: IR+RR+ALU+WR : 520, 40%4. FLOATING POINT: IR+RR+FPU+WR : 700, 10%5. BRANCH: IR+RR+ALU : 270, 20%1 cycle is 780ps = .780 nanoseconds for this machine, on the assumption thatall instructions take 1 cycle (assume all memory access is in cache). Clockfrequency is 1/.780 = 1.28 GHz (rounded to 2 decimals) for an ideal CPI=1
Who inside an organisation is responsible for deciding where in the hierarchy the information security function should reside? Why??