timescale 1 ns / 1 ps module TEST gate: reg[1:0]a, b; initial begin a-2'b00; #10 b-2'b1l; #10 a-2'bll; end initial begin b-2 b00; #40 a-2'b01; end initial #60 Stinish: endmodule Which of the following correctly represents the values of "a" and "b" at the 40th nanosecond according to the above verilog code?
timescale 1 ns / 1 ps module TEST gate: reg[1:0]a, b; initial begin a-2'b00; #10 b-2'b1l; #10 a-2'bll; end initial begin b-2 b00; #40 a-2'b01; end initial #60 Stinish: endmodule Which of the following correctly represents the values of "a" and "b" at the 40th nanosecond according to the above verilog code?
C++ Programming: From Problem Analysis to Program Design
8th Edition
ISBN:9781337102087
Author:D. S. Malik
Publisher:D. S. Malik
Chapter18: Stacks And Queues
Section: Chapter Questions
Problem 11SA
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![timescale1 ns / 1 ps
module TEST gate;
reg[1:0]a,b;
initial begin
a-2'b00; #10
b-2'bll; #10
a-2'bll;
end
initial begin
b-2'b00; #40
a-2'b01;
end
initial
#60 Cfinish;
endmodule
Which of the following correctly represents the values of "a" and "b" at the 40th nanosecond according to the above verilog code?](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Ffd82b8a1-a0ef-4f3e-b682-1867baedbf49%2F9cd4f9f4-2352-4e2e-abf2-cb4f80ae7bcc%2F5yge7ul_processed.jpeg&w=3840&q=75)
Transcribed Image Text:timescale1 ns / 1 ps
module TEST gate;
reg[1:0]a,b;
initial begin
a-2'b00; #10
b-2'bll; #10
a-2'bll;
end
initial begin
b-2'b00; #40
a-2'b01;
end
initial
#60 Cfinish;
endmodule
Which of the following correctly represents the values of "a" and "b" at the 40th nanosecond according to the above verilog code?
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