1,1II 1,1I,I| 1,1II,IV II,IV timescale lns / 1ps module mainfunction (input a,b,c, output y); assign y= (asb) |(a|c); endmodule timescale Ins / lps module testbench; reg a,b,c; mainfunction dt (.a (a),.b (b),.c(c),.y (y)); initial begin a=0; b=0; c=0; #10 if (y!==1) $display("y=logic O"); end endmodule Which of the following is true for the two verilog codes above? I. Behavioral design level is used. II. Output(y) is equal to logic 1 and the text "y=logic 0" appears in the simulation. II. The combinational circuit designed in the code includes 3 logic gates. IV. A net has to be added to the code for the output.

1,1II 1,1I,I| 1,1II,IV II,IV timescale lns / 1ps module mainfunction (input a,b,c, output y); assign y= (asb) |(a|c); endmodule timescale Ins / lps module testbench; reg a,b,c; mainfunction dt (.a (a),.b (b),.c(c),.y (y)); initial begin a=0; b=0; c=0; #10 if (y!==1) $display("y=logic O"); end endmodule Which of the following is true for the two verilog codes above? I. Behavioral design level is used. II. Output(y) is equal to logic 1 and the text "y=logic 0" appears in the simulation. II. The combinational circuit designed in the code includes 3 logic gates. IV. A net has to be added to the code for the output.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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