LIBRARY ieee; USE ieee.std logic 1164.all; ENTITY Seq_Detector_Moore IS PORT ( Clock : IN STD_LOGIC ; Resetn : IN STD _LOGIC ; w : IN STD_LOGIC ; z : OUT STD _LOGIC ) ; END Seq_Detector_Moore; ARCHITECTURE Behavior OF Seq_Detector_Moore IS TYPE state _type IS ( A, B, C) ; SIGNAL current _state, next _state : state _type; BEGIN
Task: Draw the State Diagram for the Moore Sequence Detector FSM. How many states have the New State diagram?
Given VHDL Code for the Moore Sequence Detector FSM:
LIBRARY ieee;
USE ieee.std logic 1164.all;
ENTITY Seq_Detector_Moore IS
PORT ( Clock : IN STD_LOGIC ;
Resetn : IN STD _LOGIC ;
w : IN STD_LOGIC ;
z : OUT STD _LOGIC ) ;
END Seq_Detector_Moore;
ARCHITECTURE Behavior OF Seq_Detector_Moore IS
TYPE state _type IS ( A, B, C) ;
SIGNAL current _state, next _state : state _type;
BEGIN
--next state decoder
Process (current_state, w)
BEGIN
CASE current_state IS
WHEN A =>
IF w = ’1’ THEN next _state <= A ;
ELSE next _state <= B ;
END IF ;
WHEN B =>
IF w = ’1’ THEN next _state <= A ;
ELSE next _state <= C ;
END IF ;
WHEN C =>
IF w = ’1’ THEN next _state <= A ;
ELSE next _state <= C ;
END IF ;
WHEN OTHERS =>
next_state<= A ; -- go back to the initial state
END CASE
END PROCESS ;
--state memory (FFs)
PROCESS ( Clock, Resetn )
BEGIN
IF Resetn = ’1’ THEN
current_state <= A ; --initial state
ELSIF Clock’EVENT AND Clock = ’1’ THEN
curent_state <=next_state ;
END IF;
END PROCESS;
--output decoder
z<= ’1’ WHEN current_state= C ELSE ’0’ ;
END Behavior ;
----output decoder , another way
PROCESS (current_state)
BEGIN
If curent_state=C
then z <= ’1’ ;
ELSE z <= ’0’ ;
END IF ;
END PROCESS ;
END Behavior ;
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