ask: Modify the Laser Circuit FSM to output x for 25 ns, assuming Tclk = 5 ns. Given VHDL code for the Laser Circuit FSM: library ieee; use ieee.std_logic_1164.all; entity LaserTimer is port ( b: in std_logic; x : out std_logic; clk, rst : in std_logic; ); end LaserTimer; architecture behavior of LaserTimer is type statetype is (S_Off, S_On1, S_On2, S_On3); signal currentState, nextState: statetype; begin statereg: process(clk, rst) begin if (rst=’1’) then currentstate <= S_Off; elsif (clk=’1’ and clk’event) then currentstate <= nextstate; end if; end process; comblogic: process (currentstate, b) begin case currentstate is when S_Off => x <= ‘0’; if (b=’0’) then nextstate <= S_Off; else nextstate <= S_On1; end if; when S_On1 => x <= ‘1’; nextstate <= S_On2; when S_On2 => x <= ‘1’; nextstate <= S_On3; when S_On3 => x <= ‘1’; nextstate <= S_Off; end case; end process; end behavior;
Task: Modify the Laser Circuit FSM to output x for 25 ns, assuming Tclk = 5 ns.
Given VHDL code for the Laser Circuit FSM:
library ieee;
use ieee.std_logic_1164.all;
entity LaserTimer is
port ( b: in std_logic;
x : out std_logic;
clk, rst : in std_logic;
);
end LaserTimer;
architecture behavior of LaserTimer is
type statetype is
(S_Off, S_On1, S_On2, S_On3);
signal currentState, nextState:
statetype;
begin
statereg: process(clk, rst)
begin
if (rst=’1’) then
currentstate <= S_Off;
elsif (clk=’1’ and clk’event) then
currentstate <= nextstate;
end if;
end process;
comblogic: process (currentstate, b)
begin
case currentstate is
when S_Off =>
x <= ‘0’;
if (b=’0’) then
nextstate <= S_Off;
else
nextstate <= S_On1;
end if;
when S_On1 =>
x <= ‘1’;
nextstate <= S_On2;
when S_On2 =>
x <= ‘1’;
nextstate <= S_On3;
when S_On3 =>
x <= ‘1’;
nextstate <= S_Off;
end case;
end process;
end behavior;
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