For the given VHDL program, rectify the logical and syntax errors. Highlight each error and write the corrected codes for each with justification. library ieee; use ieee. std_logic_1164; entity sample is port(a,b: in std_logic; X: out std_logic; Y: out std_logic vector(2 down to o)); end sample; architecture sample 1 of sample is begin signal R: bit:=’U’; if a=’1’ then Y<=”00”; R<=’1’; elsif b=’1’ then Y<=”01”; R<=’0’ else Y<=”11’;R<=’0’; end process; X<=R;end sample1;

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A: The code for the below question is as follows

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A: Answer: This question bases on logic gates and truth table so we have shown in the figure.

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A: ANSWER:

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A:

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A: The program for the above gievn question is fine bleow:

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