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a Test Bench file for the following VHDL code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity shiftregister is     Port ( R : in  STD_LOGIC_VECTOR(5 downto 0);            L, w, Reset : in  STD_LOGIC;            Q : out  STD_LOGIC_VECTOR(5 downto 0)); end shiftregister; architecture Behavior of shiftregister is signal Sreg : STD_LOGIC_VECTOR(5 downto 0); begin if reset='1' then Sreg <= "000000"; elsif clk'event and clk='1' then

a Test Bench file for the following VHDL code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity shiftregister is     Port ( R : in  STD_LOGIC_VECTOR(5 downto 0);            L, w, Reset : in  STD_LOGIC;            Q : out  STD_LOGIC_VECTOR(5 downto 0)); end shiftregister; architecture Behavior of shiftregister is signal Sreg : STD_LOGIC_VECTOR(5 downto 0); begin if reset='1' then Sreg <= "000000"; elsif clk'event and clk='1' then

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Create a Test Bench file for the following VHDL code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity shiftregister is
    Port ( R : in  STD_LOGIC_VECTOR(5 downto 0);
           L, w, Reset : in  STD_LOGIC;
           Q : out  STD_LOGIC_VECTOR(5 downto 0));
end shiftregister;

architecture Behavior of shiftregister is
signal Sreg : STD_LOGIC_VECTOR(5 downto 0);
begin
if reset='1' then
Sreg <= "000000";
elsif clk'event and clk='1' then
if L='1' then
Sreg <= R;
else
Sreg(0) <= Sreg(1);
Sreg(1) <= Sreg(2);
Sreg(2) <= Sreg(3);
Sreg(3) <= Sreg(4);
Sreg(4) <= Sreg(5);
Sreg(5) <= w;
end if;
end if;
Q <= Sreg;
end process;
end Behavior;

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