Draw the state diagram of the following FSM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity SimpleFSM is Port ( clock : in STD_LOGIC; P : in STD_LOGIC; reset : in STD_LOGIC; R : out STD_LOGIC); end SimpleFSM; architecture Behavioral of SimpleFSM is type state_type is (A, B, C, D); signal state: state_type; begin process (clock, reset) begin if (reset = '1') then state <= A; elsif rising_edge(clock) then case state is when A => if P = '1' then state <= B; else state <= A; end if; when B => if P = '1' then state <= C; else state <= B; end if; when C => if P = '1' then state <= D; else state <= C; end if; when D => if P = '1' then state <= B; else state <= A; end if; when others => state <= A; end case; end if; end process; R <= '1' when state = D else '0'; end Behavioral;

Computer Networking: A Top-Down Approach (7th Edition)

7th Edition

ISBN:9780133594140

Author:James Kurose, Keith Ross

Publisher:James Kurose, Keith Ross

Chapter1: Computer Networks And The Internet

Section: Chapter Questions

Problem R1RQ: What is the difference between a host and an end system? List several different types of end...

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Draw the state diagram of the following FSM:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SimpleFSM is
Port ( clock : in STD_LOGIC;
P : in STD_LOGIC;
reset : in STD_LOGIC;
R : out STD_LOGIC);
end SimpleFSM;

architecture Behavioral of SimpleFSM is
type state_type is (A, B, C, D);
signal state: state_type;

begin
process (clock, reset)
begin
if (reset = '1') then
state <= A;
elsif rising_edge(clock) then
case state is
when A =>
if P = '1' then
state <= B;
else
state <= A;
end if;
when B =>
if P = '1' then
state <= C;
else
state <= B;
end if;
when C =>
if P = '1' then
state <= D;
else
state <= C;
end if;
when D =>
if P = '1' then
state <= B;
else
state <= A;
end if;
when others =>
state <= A;
end case;
end if;
end process;
R <= '1' when state = D else '0';