Answered: Learning Outcome (4): Interpret…

Learning Outcome (4): Interpret combinational logic circuits, sequential logic circuits, register transfers, and memory and its related components as the building blocks for digital design.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Figure Q7 describes a Linear Feedback Shift Register (LFSR). Draw the equivalent schematic diagram of the system based on an off-the-shelf shift register, clearly showing the number of exclusive-OR gates needed to construct it. LIBRARY ieee; USE ieee.std logic_1164.all; entity lfsr is CLK, RESET: in STD LOGIC; Q: out STD LOGIC_VECTOR (5 downto 0) ); port ( end lfsr; architecture behavior of lfsr is begin process (CLK,RESET) begin if RESET='1' then Q <= "000001"; else Q <= ( Q(3) xor Q(2) xor Q(0) ) & Q(5 downto 1); end if; end process; end behavior;
Excersize 2: Sketch a schematic of the circuit described by the following VHDL code. Simplify the schematic so that it shows a minimum number of gates. library IEEE; use IEEE.STD LOGIC 1164.all; entity exercise2 is port (a: in y: out STD_ LOGIC_VECTOR (1 downto 0)); STD LOGIC_VECTOR (3 downto 0); end; architecture synth of exercise2 is begin process (all) begin a (0) then y <= "11"; elsif a (1) then y <= "10"; elsif a (2) then y <= "01"; elsif a (3) then y <= "00"; y <= if else a (1 downto 0); end if; end process; end;
1a. Draw a circuit diagram using appropriate logic gates to implement a 3-bit comparator. Identifythe gates used in implementation and show its usage to compare two 3-bit words by writing thetruth table. b. Write the Boolean expression for the following 4 input circuit. Include sub-expressions foroutputs of each gate. c. Complete a truth table for the previous logic gate circuit in part b. d. Write the Boolean expression for the new circuit below. Then, simplify the following logic circuitusing the theorems in Boolean algebra. Show the steps clearly and specify the law used in eachstep. Finally draw the simplified circuit diagram.
Excersize 1: Sketch a schematic of the circuit described by the following VHDL code. Simplify the schematic so that it shows a minimum number of gates. library IEEE; use IEEE.STD_LOGIC_1164.all; entity exercisel is port (a, b, c: in Y, 2: STD LOGIC; out STD LOGIC); end; architecture synth of exercisel is begin y <= (a and b and c) or (a and not b and c); z <= (a and b) or (not a and not b); end; (a and b and not c) or
10. Consider the following VHDL code. ENTITY simple IS PORT( a, b, c: IN std logic; x: OUT std logic); END simple; ARCHITECTURE arc OF simple IS BEGIN x<= (a OR (b AND NOT c)): END arc; a. How many inputs are there and what type? b. How many outputs are there and what type? c. Draw the logic circuit schematic that is equivalent to the VHDL code.
The connection diagram shows multiple gates and the pins assigned to each gate. For example, from the datasheet connection diagram of IC 7400, four individual NAND gates can be observed. Pins 1, 2 and 3 are all related to one of the four NAND gates. For each gate the top input is assigned the letter A while the bottom input is assigned B and the output is assigned the letter Y. The function tables of the ICs are normally given in terms of H (High logic level) and L (Low logic level). Referring to the datasheet function table of IC 7400 shows the four different input combinations of A and B and the corresponding output Y for one of the four NAND gates. There is also one more letter assignment that could be found in function tables, this is the letter X, a don't care assignment. In cases where an X is given, it can be replaced by either an H or L assignment without effecting the resultant functionality of the IC. An example of this case can be seen for the function table of IC 7402. The…
For the given lines of C code, show the abstract RTN or HLSM for an equivalent circuit. Draw a schematic block diagram of the circuit that does the same set of calculations. You may use more than one multiplier, adder or subtractor (do not show internal logic details). Show all registers and, if appropriate, load signals on registers. Show the combinational logic from the if statements in your circuit. Assume the registers are 32-bits. while (true) { if (A) { X = W - Y - Z; if (!B || C) { M = X*Z;
Digital Logic Design.
1-re-write the VHDL. If you faced some errors for a specific reason, please fix it. 2-synthesize it and provide the synthesized circuit. 3-do simulation and provide the waveform 4-Briefly, explain the functionality of each program.
You have to design a logic diagram which can implement the complement of following by using NAND gates ONLY. F (A, B, C, D) = Σ (0, 1, 2, 3, 6, 10, 11, 14)
(a) Write a structural Verilog code to implement the circuit shown in Figure Q3(a). X1 X3 g Z2 X2 X4 f Z3 h Z4
design Schematic diagram and verify truth table. Of given circuit