If we used lookup tables with 4 inputs and 1 output to implement the LogicModule module, how many lookup tables would be used? module LogicModule ( input logic clk, input logic Rst, input logic [7:0] DataIn, output logic [7:0] DataOut ); always @(posedge Clk) begin DataOut[7] <= DataIn[e] or DataIn[1]; DataOut[6] <= DataIn[1] or DataIn[2]; DataOut[5] <= DataIn[2] or DataIn[3]; DataOut [4] <= DataIn[3] or DataIn[4]; DataOut[3] <= DataIn[4] or DataIn[5]; DataOut [2] <= DataIn[5] or DataIn[6]; DataOut[1] <= DataIn[6] or DataIn[7]; DataOut[e] <= DataIn[7] or DataIn[0]; end endmodule

If we used lookup tables with 4 inputs and 1 output to implement the LogicModule module, how many lookup tables would be used? module LogicModule ( input logic clk, input logic Rst, input logic [7:0] DataIn, output logic [7:0] DataOut ); always @(posedge Clk) begin DataOut[7] <= DataIn[e] or DataIn[1]; DataOut[6] <= DataIn[1] or DataIn[2]; DataOut[5] <= DataIn[2] or DataIn[3]; DataOut [4] <= DataIn[3] or DataIn[4]; DataOut[3] <= DataIn[4] or DataIn[5]; DataOut [2] <= DataIn[5] or DataIn[6]; DataOut[1] <= DataIn[6] or DataIn[7]; DataOut[e] <= DataIn[7] or DataIn[0]; end endmodule

Computer Networking: A Top-Down Approach (7th Edition)

7th Edition

ISBN:9780133594140

Author:James Kurose, Keith Ross

Publisher:James Kurose, Keith Ross

Chapter1: Computer Networks And The Internet

Section: Chapter Questions

Problem R1RQ: What is the difference between a host and an end system? List several different types of end...

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Question

If we used lookup tables with 4 inputs and 1 output to implement the LogicModule module, how many lookup tables would be used?
module LogicModule
(
input logic clk,
input logic Rst,
input logic [7:0] DataIn,
output logic [7:0] DataOut
);
always @(posedge clk) begin
DataOut [7] <= DataIn[e] or DataIn[1];
DataOut[6] <= DataIn[1] or DataIn[2];
DataOut [5] <= DataIn[2] or DataIn[3];
Dataout [4] <= DataIn[3] or DataIn[4];
DataOut [3] <= DataIn [4] or DataIn[5];
Dataout [2] <= DataIn[5] or DataIn[6];
DataOut[1] <= DataIn [6] or DataIn [7];
Dataout [e] <= DataIn [7] or DataIn[0];
end
endmodule
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