What type of reset does the following code use: module Matcher ( ); input logic clk, input logic Rst, input logic DataIn, output logic Error, output logic Found logic [8:0] cnt; logic [2:0] dly; always @(posedge Clk) begin if ( Rst) begin dly <= 0; cnt <= 0; Error <= 0; Found <= 0; end else begin dly [0] <= DataIn;
What type of reset does the following code use: module Matcher ( ); input logic clk, input logic Rst, input logic DataIn, output logic Error, output logic Found logic [8:0] cnt; logic [2:0] dly; always @(posedge Clk) begin if ( Rst) begin dly <= 0; cnt <= 0; Error <= 0; Found <= 0; end else begin dly [0] <= DataIn;
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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![What type of reset does the following code use:
module Matcher
(
);
input logic clk,
input logic Rst,
input logic DataIn,
output logic Error,
output logic Found
logic [8:0] cnt;
logic [2:0] dly;
always @(posedge Clk) begin
if ( Rst) begin
dly <= 0;
cnt <= 0;
Error <= 0;
Found <= 0;
end else begin
dly [0] <= DataIn;
dly[1] <dly [0];
dly[2] <= dly[1];
cnt <= cnt + 1;
if (cnt==128 ) begin
Error <= 1;
end else begin
Error <= 0;
end
if (dly == 3'b101 ) begin
Found <= 1;
end else begin
Found <= 0;
end
end
end
endmodule
Pick one of the choices
O synchronous
O asynchronous](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F6d1ae07f-bdb5-47a8-9afa-ea5a04bdf9c8%2Feb62c45d-ac2a-4861-8f15-9794b8654c56%2F351d1db_processed.jpeg&w=3840&q=75)
Transcribed Image Text:What type of reset does the following code use:
module Matcher
(
);
input logic clk,
input logic Rst,
input logic DataIn,
output logic Error,
output logic Found
logic [8:0] cnt;
logic [2:0] dly;
always @(posedge Clk) begin
if ( Rst) begin
dly <= 0;
cnt <= 0;
Error <= 0;
Found <= 0;
end else begin
dly [0] <= DataIn;
dly[1] <dly [0];
dly[2] <= dly[1];
cnt <= cnt + 1;
if (cnt==128 ) begin
Error <= 1;
end else begin
Error <= 0;
end
if (dly == 3'b101 ) begin
Found <= 1;
end else begin
Found <= 0;
end
end
end
endmodule
Pick one of the choices
O synchronous
O asynchronous
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