H.W (3) Load the low parts of registers AX, BX,CX, and DX with constant D, C, B, A. These constants are 13h, 0001_1000b, 'M', and 14, respectively. Then load the memory location M2 with these values from registers.
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- subject : computer architectures and organization (computer science)(d) You are working on a redesign of a simple 16-bit computer which supports at most 64 kilobytes of memory. Currently, memory is word-addressed and all memory accesses load or store a 16-bit value. For example, LDA Ox6502 loads a 16-bit value from address Ox6502 into register A. The change is to support additionally 8-bit accesses, thanks to an expanded machine language (already designed by a colleague) which now supports instructions such as: ; load 16 bits from addr 6502 into A ; load 8 bits from addr 6502 into A LDAW Ox6502 LDAB Ox6502 Outline, at a high level, how you would bring about this change in the CPU design, and mentioning any difficulties you expect to encounter.[3.3] For the following C statement, write the corresponding RISC-V assembly code. Assume that the variables f, g, h, i, and j are assigned to registers x5, x6, x7, x28, and x29, respectively. Assume that the base address of the arrays A and B are in registers x10 and x11, respectively. B[8] A[i-j];
- (b) For the following C statement, write the corresponding LEGV8 assembly code. Assume that the variables f, g, h, i, and j are assigned to registers X0.X1,X2,X3, and X4, respectively. Assume that the base address of the arrays A and B are in registers X6 and X7, respectively. B[3] = A[il + Alil:Microprocessor (AVR) Fundamentals 1) - Find the contents of register R20 after each of the following codes executed. Also, indicate the state of the Z flag. (a) LDI R20, $89 LDI R21, $76 AND R20, R21 (c) LDI R20, $95 LDI R21, SAA EOR R20, R21 (b) LDI R20, 0xC5 LDI R21, 0x12 OR R20, R21 (d) LDI R20,0 LDI R21, $99 LDI R22, $FF OR R20, R21 EOR R20, R22 COM R20(c) The following Sigma 16 program has been loaded into memory at address 0000: load R3,y[RO] load R4,x[RO] lea R5, 2[RO] sub R1,R4,R3 mul R2,R1,R5 store R2,w[RO] trap RO,RO,RO x data 10 y data 12 w data 0 Show the content of the memory writing hexadecimal representation and using a table with 3 columns: the memory address, the contents of that memory address, and an explanation of what "the content (of that memory address) means". As a reference, here are the opcodes for RRR instructions: add 0, sub 1, mul 2, trap c. And here the opcodes for RX instructions: lea 0, load 1, store 2. [7]
- D] An integer arithmetic unit that can perform addition and multiplication of 16-bit unsigned numbers is to be used to multiply two 32-bit unsigned numbers. All operands, intermediate results, and final results are held in 16-bit registers labeled R0 through R15. The hardware multiplier multiplies the contents of Ri (multiplicand) by Rj (multiplier) and stores the double-length 32-bit product in registers Rj and Rj+1, with the low-order half in Rj. When j = i − 1, the product overwrites both operands. The hardware adder adds the contents of Ri and Rj and puts the result in Rj. The input carry to an Add operation is 0, and the input carry to an Add-with-carry operation is the contents of a carry flag C. The output carry from the adder is always stored in C. Specify the steps of a procedure for multiplying two 32-bit operands in registers R1, R0, and R3, R2, high-order halves first, leaving the 64-bit product in registers R15, R14, R13, and R12. Any of the registers R11 through R4 may…4. The following problems deal with translating from C code to MIPS code or MIPS code to C code. Assume that the signed variables f, g, h and i are assigned to registers $s0, $1, $2, $3 respectively. Assume the base address of the integer arrays A and B are in registers $s4 and $55 respectively. Translate the following MIPS code to C code. Please indicate which elements of integer array A and B are modified by this code. addi $t0, $1, 6 sll $t0, $t0, 4 add $t0, $t0, $5 Iw $t0, 0($t0) sw $t0, 4($4)"uppose we have the instruction Load 500. Given that memory and register R1 contain the values below: Memory Ox100 Ox600 R1 Ox200 Ox400 Охз00 ОхБ00 Ox 100 Ох600 Ox500 Ox700 Ох800 and assuming that Ra is implied in the indexed addressing mode, determine the actual value loaded into the accumulator and fill in the table below: Mode Value Loaded into AC Immediate Direct Indirect Indexed
- a) Write a single line of C code to represent the instruction leaq (rdi, r8, 2), 8rcx b) Write a single line of C code to represent the instruction movq (rax, r8, 4),8rax c) After executing the following code, which of the variables are equal to 0? (Assume ints are 32 bits wide and longs are 64 bits wide.) unsigned int a - Oxffffffff: unsigned int b = 1; unsigned int c a + b; unsigned long đ - a + D; unsigned long e = b: unsigned long f - (long) (int)a + b; (unsigned long) a CamScanner ile tarandı[1] ( Show your work. Show hoe you compute memory address by using the effective memory address computation. Assume the following values are stored at the indicated memory addresses and registers: Address Value 0x100 OxFF 0x104 OxAB 0x108 0x13 0x10c 0x11 Register %rax %rcx %rdx $0x108 (%rax) 4(%rax) 9(%rax, %rdx) 260(%rcx,%rdx) OxFC (,%rcx, 4) (%rax, %rdx, 4) Value 0x100 0x1 0x3 Fill in the following table showing the values for the indicated operands: Operand Value %rax 0x104Example: content of memory at address 3AF is 632Eu. The content of memory at address 32E# is 849FH- a. What is the instruction that will be fetched and execute. b. Show the binary operation that will be performed in AC when the instruction is executed. c. Give the contents of registers PC, AR, DR, AC, and IR at the end of instruction cycle.
