Given a system with below characteristics, answer the questions: Virtual Memory details: 1 GB virtual memory, 256 MB physical memory, page size 16K bytes TLB Details Instruction TLB, Direct-mapped, 64 virtual to physical translations Data TLB, direct-mapped 2-way associative, 128 virtual to physical translations Primary cache Details Instruction cache, cache line size is 32 bytes, 2-way associative, 4 KB of instructions in the cache, LRU replacement Data cache, cache line size is 64 bytes, direct-mapped, 8 KB of data in the cache, write-through / no-write allocate Secondary cache Details cache line size is 512 bytes, 4-way associative, 1 MB of instructions or data in cache (unified cache), LRU replacement, write-back / write allocate Questions: How many sets are in the secondary cache? How many bits are required for the tag to access the secondary cache? How many sets are in the instruction cache? How many bits are required for the tag to access the instruction cache?
Given a system with below characteristics, answer the questions: Virtual Memory details: 1 GB virtual memory, 256 MB physical memory, page size 16K bytes TLB Details Instruction TLB, Direct-mapped, 64 virtual to physical translations Data TLB, direct-mapped 2-way associative, 128 virtual to physical translations Primary cache Details Instruction cache, cache line size is 32 bytes, 2-way associative, 4 KB of instructions in the cache, LRU replacement Data cache, cache line size is 64 bytes, direct-mapped, 8 KB of data in the cache, write-through / no-write allocate Secondary cache Details cache line size is 512 bytes, 4-way associative, 1 MB of instructions or data in cache (unified cache), LRU replacement, write-back / write allocate
Questions:
How many sets are in the secondary cache?
How many bits are required for the tag to access the secondary cache?
How many sets are in the instruction cache?
How many bits are required for the tag to access the instruction cache?
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