Assume that L1 cache can be written with 16 bytes every 4 processor cycle, the time to receive the first 16 byte block from the memory controller is 120 cycles, each additional 16 byte block from main memory requires 16 cycles and data can be bypassed directly into the read port of the L1 cache. How many cycles would it take to service an L1 cache miss.

Assume that L1 cache can be written with 16 bytes every 4 processor cycle, the time to receive the first 16 byte block from the memory controller is 120 cycles, each additional 16 byte block from main memory requires 16 cycles and data can be bypassed directly into the read port of the L1 cache. How many cycles would it take to service an L1 cache miss.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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