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DataPath Performance Evaluation: Use the following information for all parts of the question. Please round your answers to 2 decimal places. Memory Access = 680 ps ALU Operations = 340 ps Register Access = 170 ps Note: for this exam, the critical data path for JUMP is just the Instruction Fetch stage. 1. If we implement the DataPath as a single-cycle using variable cycle length, fill in the cycle time for the following statement types (critical data path) in ps. R-Type:: Load Type = Store Type = Branch Type = Jump = = ps ps ps ps ps

DataPath Performance Evaluation: Use the following information for all parts of the question. Please round your answers to 2 decimal places. Memory Access = 680 ps ALU Operations = 340 ps Register Access = 170 ps Note: for this exam, the critical data path for JUMP is just the Instruction Fetch stage. 1. If we implement the DataPath as a single-cycle using variable cycle length, fill in the cycle time for the following statement types (critical data path) in ps. R-Type:: Load Type = Store Type = Branch Type = Jump = = ps ps ps ps ps

Database System Concepts
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
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Please help with this Computer architecture homework question.
# DataPath Performance Evaluation #### Instructions: Use the following information for all parts of the question. Please round your answers to two decimal places. - **Memory Access** = 680 ps - **ALU Operations** = 340 ps - **Register Access** = 170 ps **Note:** For this exam, the critical data path for JUMP is just the Instruction Fetch stage. --- ### Questions: 1. **If we implement the DataPath as a single-cycle using variable cycle length, fill in the cycle time for the following statement types (critical data path) in ps.** - **R-Type**: ______ ps - **Load Type**: ______ ps - **Store Type**: ______ ps - **Branch Type**: ______ ps - **Jump**: ______ ps 2. **If we implement the above DataPath using a single-cycle with fixed length, the cycle length would be ________ ps.** 3. **If we are running a program with the following instruction mix:** - **R-type**: 48% - **Load type**: 19% - **Store type**: 23% - **Branch type**: 8% - **Jump**: 2% Fill in the table: | TYPE | %age | Critical Time | Weighted Time | |---------|------|---------------|---------------| | R-Type | 48% | | | | Load | 19% | | | | Store | 23% | | | | Branch | 8% | | | | Jump | 2% | | | 4. **The average time** to execute an instruction is ________ ps.
Transcribed Image Text:# DataPath Performance Evaluation #### Instructions: Use the following information for all parts of the question. Please round your answers to two decimal places. - **Memory Access** = 680 ps - **ALU Operations** = 340 ps - **Register Access** = 170 ps **Note:** For this exam, the critical data path for JUMP is just the Instruction Fetch stage. --- ### Questions: 1. **If we implement the DataPath as a single-cycle using variable cycle length, fill in the cycle time for the following statement types (critical data path) in ps.** - **R-Type**: ______ ps - **Load Type**: ______ ps - **Store Type**: ______ ps - **Branch Type**: ______ ps - **Jump**: ______ ps 2. **If we implement the above DataPath using a single-cycle with fixed length, the cycle length would be ________ ps.** 3. **If we are running a program with the following instruction mix:** - **R-type**: 48% - **Load type**: 19% - **Store type**: 23% - **Branch type**: 8% - **Jump**: 2% Fill in the table: | TYPE | %age | Critical Time | Weighted Time | |---------|------|---------------|---------------| | R-Type | 48% | | | | Load | 19% | | | | Store | 23% | | | | Branch | 8% | | | | Jump | 2% | | | 4. **The average time** to execute an instruction is ________ ps.
**Memory Performance:** The following questions will refer to the same instruction mix as above, with the following additional information: **Processor P1:** - 42% of all instructions are memory access instructions. - Level 1 Cache Access = 0.68 ns - Main Memory Access = 59 ns - 12% of all memory access is a "miss". --- **Questions:** 9. The clock rate of the processor = ________ GHz. 10. The **Average Memory Access Time** for the given data = ________ ns. 11. The **Average number of cycles** for a memory access = ________ cycles. 12. Assuming that the base CPI = 1.0 cycles, and using the answer from #11, the average time to complete an instruction for the program described = ________ ns. --- **Now, consider processor P2, with the addition of a Level 2 Cache, with an access time of 4.3 ns and a "hit" rate of 13%.** 13. The **Average Memory Access Time** for the given data = ________ ns. 14. The **Average number of cycles** for a memory access = ________ cycles. 15. Assuming that the base CPI = 1.0 cycles, and using the answer from #14, the average CPI for the program described = ________ cycles. 16. Which processor performs better for the program described? (P1 or P2) ________ 17. Including the delays in the Pipelined DataPath in question 8, and the memory performance analysis in question 15, find the Average Memory Access = ________ ns for P2. 18. Find the final average effective number of cycles for processor P2 = ________ 19. Find the final average time to complete an instruction for processor P2 = ________
Transcribed Image Text:**Memory Performance:** The following questions will refer to the same instruction mix as above, with the following additional information: **Processor P1:** - 42% of all instructions are memory access instructions. - Level 1 Cache Access = 0.68 ns - Main Memory Access = 59 ns - 12% of all memory access is a "miss". --- **Questions:** 9. The clock rate of the processor = ________ GHz. 10. The **Average Memory Access Time** for the given data = ________ ns. 11. The **Average number of cycles** for a memory access = ________ cycles. 12. Assuming that the base CPI = 1.0 cycles, and using the answer from #11, the average time to complete an instruction for the program described = ________ ns. --- **Now, consider processor P2, with the addition of a Level 2 Cache, with an access time of 4.3 ns and a "hit" rate of 13%.** 13. The **Average Memory Access Time** for the given data = ________ ns. 14. The **Average number of cycles** for a memory access = ________ cycles. 15. Assuming that the base CPI = 1.0 cycles, and using the answer from #14, the average CPI for the program described = ________ cycles. 16. Which processor performs better for the program described? (P1 or P2) ________ 17. Including the delays in the Pipelined DataPath in question 8, and the memory performance analysis in question 15, find the Average Memory Access = ________ ns for P2. 18. Find the final average effective number of cycles for processor P2 = ________ 19. Find the final average time to complete an instruction for processor P2 = ________
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