Please help with this Computer architecture homework question. Memory Performance:The following questions will refer to the same instruction mix as above, with the followingadditional information:Processor P1:42% of all instructions are memory access instructions.Level 1 Cache Access = 0.68 nsqys-boodMain Memory Access = 59 ns12% of all memory access is a "miss".9. The clock rate of the processor =GHz.10 The Average Memory Access Time for the given data =11. The Average number of cycles for a memory access =cycles12. Assuming that the base CPI = 1.0 cycles, and using the answer from #11, momolami swo990012nsmenimse of griensthe verage time to complete an instruction for the program described =Now, consider processor P2, with the addition of a Level 2 Cache, with an access time ofob bazilogi adt of f4.3 ns and a "hit" rate of 13%.nsns for P2.13. The Average Memory Access Time for the given data =cycles and murgo novig on T14. The Average number of cycles for a memory access =om ancitourtani beold) to15. Assuming that the base CPI = 1.0 cycles, and using the answer from #14, (slabo ganlups)yag events aquest bus batoibosqimalle als cycles dondolothe average CPI for the program described =ino-stupor16. Which processor performs better for the program described? (P1 or P2)sollai 19q17. Including the delays in the Pipelined DataPath in question 8, and the memoryperformance analysis in question 15, find theAverage Memory Access =18. Find the final average effective number of cycles for processor P2 =19. Find the final average time to complete an instruction for processor P2 =_3971

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Description: Please help with this Computer architecture homework question. Memory Performance:The following questions will refer to the same instruction mix as above, with the followingadditional information:Processor P1:42% of all instructions are memory access

Clock Rate:The clock rate, measured in Hertz (Hz) or Gigahertz (GHz), represents the speed at which…

Engineering

Computer Science

Memory Performance: The following questions will refer to the same instruction mix as above, with the following additional information: Processor P1: 42% of all instructions are memory access instructions. Level 1 Cache Access=0.68 ns Main Memory Access - 59 ns 12% of all memory access is a "miss". 9. The clock rate of the processor = 10 The Average Memory Access Time for the given data- GHz. ns _cycles 11. The Average number of cycles for a memory access = 12. Assuming that the base CPI = 1.0 cycles, and using the answer from #11, the average time to complete an instruction for the program described ns 8

Memory Performance: The following questions will refer to the same instruction mix as above, with the following additional information: Processor P1: 42% of all instructions are memory access instructions. Level 1 Cache Access=0.68 ns Main Memory Access - 59 ns 12% of all memory access is a "miss". 9. The clock rate of the processor = 10 The Average Memory Access Time for the given data- GHz. ns _cycles 11. The Average number of cycles for a memory access = 12. Assuming that the base CPI = 1.0 cycles, and using the answer from #11, the average time to complete an instruction for the program described ns 8

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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