Fill in all blank spaces. All miss penalties should be rounded to the nearest integer. All CPI values should be rounded to one decimal place, if needed. Suppose the following is true about a CPU: It has only L1 cache . The base CPI is 1.5 The clock rate is 2.5 GHz . The memory access time is 250 ns . The miss rate per instruction at L1 cache is 4% The cache miss penalty is cycles. The new effective CPI is Now suppose the following about the same CPU: . It also has L2 cache • Access time for L2 cache is 13 ns . The miss rate to main memory is reduced by 0.3% The miss penalty for an L1 miss with an L2 hit is The miss penalty for an L1 miss with an L2 miss is The new total CPI in this case is cycles. cycles.

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
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Chapter1: Introduction
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Fill in all blank spaces.
All miss penalties should be rounded to the nearest integer.
All CPI values should be rounded to one decimal place, if needed.
Suppose the following is true about a CPU:
It has only L1 cache
. The base CPI is 1.5
• The clock rate is 2.5 GHz
. The memory access time is 250 ns
• The miss rate per instruction at L1 cache is 4%
The cache miss penalty is
cycles.
The new effective CPI is
Now suppose the following about the same CPU:
• It also has L2 cache
• Access time for L2 cache is 13 ns
. The miss rate to main memory is reduced by 0.3%
The miss penalty for an L1 miss with an L2 hit is
The miss penalty for an L1 miss with an L2 miss is
The new total CPI in this case is
cycles.
cycles.
Transcribed Image Text:Fill in all blank spaces. All miss penalties should be rounded to the nearest integer. All CPI values should be rounded to one decimal place, if needed. Suppose the following is true about a CPU: It has only L1 cache . The base CPI is 1.5 • The clock rate is 2.5 GHz . The memory access time is 250 ns • The miss rate per instruction at L1 cache is 4% The cache miss penalty is cycles. The new effective CPI is Now suppose the following about the same CPU: • It also has L2 cache • Access time for L2 cache is 13 ns . The miss rate to main memory is reduced by 0.3% The miss penalty for an L1 miss with an L2 hit is The miss penalty for an L1 miss with an L2 miss is The new total CPI in this case is cycles. cycles.
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