ILP (Instruction Level Parallelism) processors have the same execution hardware as RISC (Reduced Instruction Set Architecture) processors. The machines without ILP have complex hardware which is hard to implement. A typical ILP allows multiple-cycle operations to be pipelined. Suppose, 4 operations can be carried out in single clock cycle. So there will be 4 functional units, each attached to one of the operations, branch unit, and common register file in the ILP execution hardware. The sub-operations that can be performed by the functional units are Integer ALU, Integer Multiplication, Floating Point Operations, Load, Store. Let the respective latencies be 1, 2, 3, 2, 1.. Let the sequence of instructions be 1. y1 = x1*1010 2. y2 = x2*1100 3. z1 = y1+0010 4. z2 = y2+0101 5. t1 = t1+1 6. p = q*1000 7. clr = clr+0010 8. r = r+0001 Compare with a table, the Sequential record of execution vs. Instruction-level Parallel record of execution Explain your table
ILP (Instruction Level Parallelism) processors have the same execution hardware as RISC (Reduced Instruction Set Architecture) processors. The machines without ILP have complex hardware which is hard to implement. A typical ILP allows multiple-cycle operations to be pipelined.
Suppose, 4 operations can be carried out in single clock cycle. So there will be 4 functional units, each attached to one of the operations, branch unit, and common register file in the ILP execution hardware. The sub-operations that can be performed by the functional units are Integer ALU, Integer Multiplication, Floating Point Operations, Load, Store. Let the respective latencies be 1, 2, 3, 2, 1..
Let the sequence of instructions be
1. y1 = x1*1010
2. y2 = x2*1100
3. z1 = y1+0010
4. z2 = y2+0101
5. t1 = t1+1
6. p = q*1000
7. clr = clr+0010
8. r = r+0001
Compare with a table, the Sequential record of execution vs. Instruction-level Parallel record of execution
Explain your table
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