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Consider a multi-level memory management scheme with the following format for virtùal addresses: Virtual Page # (10 bits) Virtual Page # (20 bits) Offset (12 bits) Virtual addresses are translated into physical addresses of the following form: Physical Page # (20 bits) Offset (12 bits) Page table entries (PTE) are 32 bits in the following format, stored in big-endian form in memory (i.e., the MSB is first byte in memory): OS Physical Page# (20 bits) defined (3 bits) Here, "Virtual" means that a translation is valid, "Writeable" means that the page is writeable, "User" means that the page is accessible by the User (rather than only by the Kernel). Note: the phrase "page table" in the following questions means the multi-level data structure that maps virtual addresses to physical addresses. (b) Suppose that we want an address space with one physical page at the top of the address space and one physical page at the bottom of the address space. How big would the page table be (in bytes)? (a) How big is a page? (c) What is the maximum size of a page table (in bytes) for this scheme?

Consider a multi-level memory management scheme with the following format for virtùal addresses: Virtual Page # (10 bits) Virtual Page # (20 bits) Offset (12 bits) Virtual addresses are translated into physical addresses of the following form: Physical Page # (20 bits) Offset (12 bits) Page table entries (PTE) are 32 bits in the following format, stored in big-endian form in memory (i.e., the MSB is first byte in memory): OS Physical Page# (20 bits) defined (3 bits) Here, "Virtual" means that a translation is valid, "Writeable" means that the page is writeable, "User" means that the page is accessible by the User (rather than only by the Kernel). Note: the phrase "page table" in the following questions means the multi-level data structure that maps virtual addresses to physical addresses. (b) Suppose that we want an address space with one physical page at the top of the address space and one physical page at the bottom of the address space. How big would the page table be (in bytes)? (a) How big is a page? (c) What is the maximum size of a page table (in bytes) for this scheme?

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Consider a multi-level memory management scherne with the following format for virtual addresses: Virtual Page # (10 bits) Virtual Page # Offset (20 bits) (12 bits) Virtual addresses are translated into physical addresses of the following form: Physical Page # (20 bits) Offset (12 bits) Page table entries (PTE) are 32 bits in the following format, stored in big-endian formin memory (i.e., the MSB is first byte in memory): Physical Page# (20 bits) OS defined (3 bits) Here, "Virtual" means that a translation is valid, "Writeable" means that the page is writeable, "User" means that the page is accessible by the User (rather than only by the Kernel). Note: the phrase “page table" in the following questions means the multi-level data structure that maps virtual addresses to physical addresses. (b) Suppose that we want an address space with one physical page at the top of the address space and one physical page at the bottom of the address space. How big would the page table be (in bytes)? (a) How big is a page? (c) What is the maximum size of a page table (in bytes) for this scheme? Valid ----- Writeable User --- Write
Transcribed Image Text:Consider a multi-level memory management scherne with the following format for virtual addresses: Virtual Page # (10 bits) Virtual Page # Offset (20 bits) (12 bits) Virtual addresses are translated into physical addresses of the following form: Physical Page # (20 bits) Offset (12 bits) Page table entries (PTE) are 32 bits in the following format, stored in big-endian formin memory (i.e., the MSB is first byte in memory): Physical Page# (20 bits) OS defined (3 bits) Here, "Virtual" means that a translation is valid, "Writeable" means that the page is writeable, "User" means that the page is accessible by the User (rather than only by the Kernel). Note: the phrase “page table" in the following questions means the multi-level data structure that maps virtual addresses to physical addresses. (b) Suppose that we want an address space with one physical page at the top of the address space and one physical page at the bottom of the address space. How big would the page table be (in bytes)? (a) How big is a page? (c) What is the maximum size of a page table (in bytes) for this scheme? Valid ----- Writeable User --- Write
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