Draw the state diagram for a clocked synchronous state machine with two inputs, INIT and X, and one Moore-type output Z. As long as INIT is asserted, Z remains 0. Once INIT is negated, Z should remain 0 until X has been 0 for two consecutive ticks and 1 for two successive ticks (or vice versa). Then Z should go to 1 and remain 1 until INIT is asserted again. Assume that once INIT is negated, it will not be asserted again until sometime after Z goes to a 1. (Hint: No more than ten states are required.)

Draw the state diagram for a clocked synchronous state machine with two inputs, INIT and X, and one Moore-type output Z. As long as INIT is asserted, Z remains 0. Once INIT is negated, Z should remain 0 until X has been 0 for two consecutive ticks and 1 for two successive ticks (or vice versa). Then Z should go to 1 and remain 1 until INIT is asserted again. Assume that once INIT is negated, it will not be asserted again until sometime after Z goes to a 1. (Hint: No more than ten states are required.)

Computer Networking: A Top-Down Approach (7th Edition)

7th Edition

ISBN:9780133594140

Author:James Kurose, Keith Ross

Publisher:James Kurose, Keith Ross

Chapter1: Computer Networks And The Internet

Section: Chapter Questions

Problem R1RQ: What is the difference between a host and an end system? List several different types of end...

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1. Draw the state diagram for a clocked synchronous state machine with two inputs, INIT and X, and
one Moore-type output Z. As long as INIT is asserted, Z remains 0. Once INIT is negated, Z should
remain 0 until X has been 0 for two consecutive ticks and 1 for two successive ticks (or vice versa).
Then Z should go to 1 and remain 1 until INIT is asserted again. Assume that once INIT is negated,
it will not be asserted again until sometime after Z goes to a 1.
(Hint: No more than ten states are required.)

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