Write VHDL code for this FSM. Add an asynchronous RESET, active High to the state diagram. ### State Transition TableThis table represents a state transition system, often used in digital design and computer science for modeling finite state machines (FSMs). The table comprises the following components:#### Columns:1. **Present State**: The current state of the system, depicted in binary form (e.g., S0=000).2. **Next State (X=0)**: The state the system transitions to when the input X is 0.3. **Next State (X=1)**: The state the system transitions to when the input X is 1.4. **Output z**: The output of the system for the given present state.#### Rows:- **S0=000**: - Next State for X=0: S0 - Next State for X=1: S1 - Output z: 0- **S1=001**: - Next State for X=0: S2 - Next State for X=1: S3 - Output z: 0- **S2=010**: - Next State for X=0: S4 - Next State for X=1: S2 - Output z: 0- **S3=011**: - Next State for X=0: S4 - Next State for X=1: S2 - Output z: 0- **S4=100**: - Next State for X=0: S0 - Next State for X=1: S0 - Output z: 1#### Unused States:- States such as (101, 110, 111) are unused in this FSM design. If reached, they default to: - Next State for X=0: S0 - Next State for X=1: S0 - Output z: 0This structured table helps clarify how the states transition based on input, and what output is generated at each step. Understanding these transitions is critical for designing and implementing effective state machines.

Solution :: Let's see Frist what is VHDL code is actually ? Answer :: A VHSIC Hardware Description Language (VHDL) is an hardware description language (HDL) that can model the behavior and structure of the digital systems at multiple levels of the abstraction, ranging from the system level down to that of logic gates, for a design entry, documentation, and the verification purposes. Now let's see the above question in breaking down into two parts first a) Write VHDL code for this FSM. b) Add an asynchronous RESET, active High to the state diagram. This is how will answer the complete question by breaking it's complexity in subquestion so you can understand easily ... a) Write VHDL code for this FSM. Answer:: Code :: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity VHDL_MOORE_FSM is port ( clock: in std_logic; --- clock signal reset: in std_logic; -- active high async reset input X : in std_logic; -- binary sequence input Z : out std_logic -- output of the VHDL FSM ); end VHDL_MOORE_FSM; architecture Behavioral of VHDL_MOORE_FSM is type MOORE_FSM is (S0,S1,S2,S3,S4); signal current_state, next_state: MOORE_FSM; begin -- Sequential memory of the VHDL MOORE FSM process(clock,reset) begin if(reset='1') then current_state <= S0; --initial state considered as S0 elsif(rising_edge(clock)) then current_state <= next_state; end if; end process;-- Next state logic of the VHDL MOORE FSM Sequence Detector -- Combinational logic process(current_state,X) begin case(current_state) is when S0=> if(X='1') then -- "1" next_state <= S1; else next_state <= S0; end if; when S1 => if(X='1') then -- "1" next_state <= S3; else next_state <= S2; end if; when S2 => if(X='1') then -- "1" next_state <= S2; else next_state <= S4; end if; when S3 => if(X='1') then -- "1" next_state <= S2; else next_state <= S4; end if; when S4=> next_state <= S0; when others => next_state <= S0; end case; end process;-- Output logic of the VHDL MOORE FSM process(current_state) begin case current_state is when S0=> Z <= '0'; when S1=> Z <= '0'; when S2=> Z <= '0'; when S3=> Z <= '0'; when S4=> Z <= '1'; when others => Z <= '0'; end case; end process; end Behavioral;b) Add an asynchronous RESET, active High to the state diagram. Answer :: Thank you ... If you have any doubts please feel free to ask the doubts will solved it ...