Consider the following assumptions: Size of virtual address: 64 bits Size of physical address: 40 bits Page size: 4 KB Size of meta data per page table entry: 8 bits What is the size of the page table for this system?
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- Consider the main memory size of 128 kB, Cache size of 16 kB, Block size of 256 B with Byte addressable memory. What is the physical address split for 2-way, 4-way and 8-way set associative?Consider a virtual memory system with a 50-bit logical address and a 38-bit physical address. Suppose that the page/frame size is 16K bytes. Assume that each page table entry is 4 Bytes. a. How many frames are in the systems? a.How many pages in the virtual address space for a process? b. If a single-level page table is deployed, calculate the size of the page table for each process c. Design a multilevel page table structure for this system to ensure that each page table can fit into one frame. How many levels is needed? Draw a figure to show your page systems;A system has 4-kB pages, a 48-bit virtual address space, and a 33-bit physical address space. Assuming that page tables contain only physical page numbers--that is, no meta-data--that it is implemented as a simple lookup table, and that physical page numbers are packed into the smallest number of 8-bit bytes that can hold them (there may be wasted bits at each entry), how many bytes of memory are required to hold the entire page table? Please enter your answer in bytes.
- Suppose a byte-addressable computer using set associative cache has 2^24 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?Question 16 Suppose we have a virtual address space of 8 kilobytes (KB), a physical memory size of 6 kilobytes (KB) that uses byte addressing, and a page. size of 3 kilobytes (KB). There is no cache in the system. What are the sizes of the page and offset fields in the virtual address? a. page field; 3 bits and offset field: 10 bits b. page field: 2 bits and offset field: 11 bits c page field: 10 bits and offset field: 3 bits d. page field: 8 bits and offset field: 4 bits e. None of the other answers.Suppose a byte-addressable computer using set associative cache has 4Mbyes of main memory and a cache of 64 blocks, where each cache block contains 8 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache? Show all work and explain how you got the answers please. Thanks
- Consider a word addressable system. The main memory is of size 2 MB and direct-mapped cache containing 1024 lines. The size of block is 16 bytes while each word consists of 2 bytes. What is the tag for memory address (AF9CB)H?We consider a virtual memory design for a computer architecture. Suppose that the byte- addressed computer has 256 bytes pages, 16-bit virtual addresses, and 16-bit page table entries (PTE) (NUM 1 bits of one PTE are used for reference, valid checking, protection mechanism, etc.). The computer uses two-level hierarchical page tables. 1. How many virtual pages can be addressed by the architecture? 2. What is the maximal size of the physical memory that can be supported by the architec- ture? 3. We are now running a program which is using 300 bytes of memory currently. What is the smallest possible number of PTES to store the running program?Question 28 3 pts Figure below shows an "inverted page table architecture" for memory management. Select the correct answers to the following questions: A: How many page table entries (i.e., rows) should exist in the "page table"? B: What are the subparts of the "logical address"? logical address physical address CPU physical memory page table O A: Page table entries are equal to the number of the physical memory frames. B: page number, displacement, page table address O A: Page table entries are equal to the number of the physical memory frames. B: Process ID, page number, displacement O A: Page table entries are equal to the number of the pages in the program's logical address space. B: Process control block, Process ID, displacement. O A: Page table entries are equal to the number of the pages in the program's logical address space. B: Process ID, page number, displacement < Previous Next ▸
- I need the answer as soon as possibleA computer system has an L1 cache, an L2 cache, and a main memory unit 10.4k view= connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times are 2 nanoseconds, 20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and the main memory unit respectively. Data Data Bus Bus L1 L2 Main Cache Cache Memory 4 words 4 words When there is a miss in both L1 cache and L2 cache, first a block is transferred from main memory to L2 cache, and then a block is transferred from L2 cache to L1 cache. What is the total time taken for these transfers?For a direct-mapped cache design with a 32-bit address, the following bitsof the address are used to access the cache. Use the table below. a. What is the cache block size (in words)?b. How many entries does the cache have?c. What is the ration between total bits required for such a cache implementation overthe data storage bit?