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Consider a pipeline that has 5 stages: (1) instruction fetch – 200 ps, (2) instruction decode - 100 ps, (3) instruction execution – 200 ps, (4) memory read – 200 ps, (5) register write – 100 ps | a. If the machine is not pipelined, but the latencies for the various operations involved in instruction fetch and execute are the same as above, what is the latency of a single instruction? (Assume all steps must occur). b. What is the latency of an instruction flowing through the pipeline? c. What is the execution time of a 100 instruction program without pipelining?

Consider a pipeline that has 5 stages: (1) instruction fetch – 200 ps, (2) instruction decode - 100 ps, (3) instruction execution – 200 ps, (4) memory read – 200 ps, (5) register write – 100 ps | a. If the machine is not pipelined, but the latencies for the various operations involved in instruction fetch and execute are the same as above, what is the latency of a single instruction? (Assume all steps must occur). b. What is the latency of an instruction flowing through the pipeline? c. What is the execution time of a 100 instruction program without pipelining?

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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2. Consider a pipeline that has 5 stages: (1) instruction fetch – 200 ps, (2) instruction decode - 100 ps, (3) instruction execution – 200 ps, (4) memory read – 200 ps, (5) register write – 100 ps a. If the machine is not pipelined, but the latencies for the various operations involved in instruction fetch and execute are the same as above, what is the latency of a single instruction? (Assume all steps must occur). b. What is the latency of an instruction flowing through the pipeline? c. What is the execution time of a 100 instruction program without pipelining?
Transcribed Image Text:2. Consider a pipeline that has 5 stages: (1) instruction fetch – 200 ps, (2) instruction decode - 100 ps, (3) instruction execution – 200 ps, (4) memory read – 200 ps, (5) register write – 100 ps a. If the machine is not pipelined, but the latencies for the various operations involved in instruction fetch and execute are the same as above, what is the latency of a single instruction? (Assume all steps must occur). b. What is the latency of an instruction flowing through the pipeline? c. What is the execution time of a 100 instruction program without pipelining?
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