Translate the following user-level instruction to a microprogram so it can be directly executed by the vertical architecture (VA) attached. 1.b Also show the opcode and register representation in hexadecimal for each finding VA instruction. B := D – BAND(C+D) if B < 0 GOTO 70;
Translate the following user-level instruction to a microprogram so it can be directly executed by the vertical architecture (VA) attached. 1.b Also show the opcode and register representation in hexadecimal for each finding VA instruction. B := D – BAND(C+D) if B < 0 GOTO 70;
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Translate the following user-level instruction to a microprogram so it can be directly executed by the vertical architecture (VA) attached. 1.b Also show the opcode and register representation in hexadecimal for each finding VA instruction.
B := D – BAND(C+D) if B < 0 GOTO 70;
![VERTICAL MICROARCHITECTURE
16
R1
decoder
AND
16, R2
decoder
Clock
Subcycles
16
registers
Mmux
A latch
B latch
Increment
MPC
MAR
256x 12
Control
store
MBR
Micro
seq.
logic
Amux
MIR
NZ
ALU
OP R1 R2
OP
Decode
Shifter
RD
WR
Fig. 4-18. A microarchitecture with vertical microinstructions.
Example of OP Assignment for Vertical Architecture
OP Instruction
8 IFZ GOTO X;
9 X;= X+ Y;
10 X:= BAND(X, Y); R1 <- X, R2 <- Y
11 X:= Y;
12 X:= NOT (Y);
13 X:= RSHIFT (Y);
14 X:= LSHIFT (Y);
15 MAR := X;
MBR := Y; WR;
Register Assignment
OP Instruction
MAR := X;
Register Assignment
R1 <-X
R1, R2 <-X
R1 <- X, R2 <- Y
1 X:= MBR;
2 RD;
R1 <-X
NA
R1 <- X, R2 <- Y
R1 <- X, R2 <- Y
R1 <- X, R2 <- Y
R1 <- X, R2 <- Y
R1 <- X, R2 <- Y
3
WR;
NA
4
MBR := X;
R2 < -X
5 ALU :X;
R2 <-X
NZ;
6 GOTO X;
IFN GOTO X;
R1, R2 <- X
7
R1, R2 <- X
O Focus
W](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F14c432fb-49ed-49ed-a7d2-bd3c5f79fdeb%2F9e38318a-0b92-41e4-8bbd-6e2d4f8df6b2%2Flvq64v_processed.png&w=3840&q=75)
Transcribed Image Text:VERTICAL MICROARCHITECTURE
16
R1
decoder
AND
16, R2
decoder
Clock
Subcycles
16
registers
Mmux
A latch
B latch
Increment
MPC
MAR
256x 12
Control
store
MBR
Micro
seq.
logic
Amux
MIR
NZ
ALU
OP R1 R2
OP
Decode
Shifter
RD
WR
Fig. 4-18. A microarchitecture with vertical microinstructions.
Example of OP Assignment for Vertical Architecture
OP Instruction
8 IFZ GOTO X;
9 X;= X+ Y;
10 X:= BAND(X, Y); R1 <- X, R2 <- Y
11 X:= Y;
12 X:= NOT (Y);
13 X:= RSHIFT (Y);
14 X:= LSHIFT (Y);
15 MAR := X;
MBR := Y; WR;
Register Assignment
OP Instruction
MAR := X;
Register Assignment
R1 <-X
R1, R2 <-X
R1 <- X, R2 <- Y
1 X:= MBR;
2 RD;
R1 <-X
NA
R1 <- X, R2 <- Y
R1 <- X, R2 <- Y
R1 <- X, R2 <- Y
R1 <- X, R2 <- Y
R1 <- X, R2 <- Y
3
WR;
NA
4
MBR := X;
R2 < -X
5 ALU :X;
R2 <-X
NZ;
6 GOTO X;
IFN GOTO X;
R1, R2 <- X
7
R1, R2 <- X
O Focus
W
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