Complete the following truth table for an Active Low Decoder 2x4. En Al Ao D3 Dz D1 Do 1 X X 0 0 0 0 0 1 0 1 0 0 1 1
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Q: question number 25
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- Perform the following functions:a. What will be the parity of the data signal to send as even parity:10100111001b. (0101)BCD = (---?---)2 = (---?---)Excess-3 = (---?---)Grayc. How to represent following numbers in signed representation:1. (-78)102. (-19)10Please answer all subpart All is compulsory pleasei. Draw the circuit in the figure below. Complete connection for making seven segment decoder and write the truth table of BCD to seven segment display. VCC T CONNECTION DIAGRAM DIP (TOP VIEW) 1 CC Vcc 15 7447 _1_2_3_4_5_8_7_8 в с LT BI/RBO RBI DA GND GND = d e с g 2000 CA b D -b a CA
- parity generator design, construct and test a circuit that generates an even parity bit ffrom four messages bits . use XOR gates. adding one more XOR gate, expand the circuit so that it generates an odd parity bit also.Write VHDL code for a modulo-13 counter (counting sequence is 010, 110, …. 1210). The counter has the following features: a synchronous Active High Reset a value R can be loaded into the counter, using the signal Ld (Load) The signal Ld is active High Draw the schematic of your counter, showing the inputs and outputs. Show the number of bits for R, Q (output of the counter), Ld.Assuming even parity, find the parity bit for each of the following data units. a. 1001010 b. 0001101 c. 1000000 d. 1110111
- a) i) Determine the number of bits per level required when using FSK with 4 different frequencies and QAM with a constellation of 256 points. ii) We want to digitise a signal that contains frequencies between 100 Hz and 1500 Hz, assuming 16 bits per sample. The digitised signal will be transmitted using a QPSK process. Determine the bit rate and the level rate. iii) We need to send 210,000 bits per second over a noiseless channel using 128- QAM. Determine the required bandwidth.a- vvnat Ts the testSOR. at are the metions of &dienlay Smonitor Sfinich2. c- How to generate a clock signal with T=10ns?- What is meant by 4 to 16-line decoder? Draw the block diagram of that decoder (Please don't show the logic circuit) that has active HIGH inputs and active LOw outputs. - Draw the decoding logic circuit that will detect following binary codes. Given that an active HIGH output is required. (i) 1101 (ii) 110010 - You wish to detect only the presence of the codes 1110, 1101, 0111 and 1111. An active HIGH output is required to indicate their presence. Develop the minimum decoding logic with a single output that will indicate when any one of these codes is on the inputs. For any other codes output must be LOW. -For the decimal to BCD encoder logic of the following circuit, assume that the inputs 5, 7 and 9 are HIGH. What is the output code? Is it a valid BCD code? A, 4567