Ch04.2. Consider the following assembly language code: 10: lw $30, value I1: add $31, $30, $a1 12: add $t1,$t1, Sal 13: lw $t7, ($30) 14: bnez St7, loop 15: add $t1,$t1, $30 16: add $t2, $30, $t4 17: add $t3, $t2, $t5 Consider a pipeline with forwarding, hazard detection, and 1 delay slot for branches. The pipeline is the typical 5-stage IF, ID, EX, MEM, WB MIPS design. For the above code, complete the pipeline diagram below (instructions on the left, cycles on top) for the code. Insert the characters IF, ID, EX, MEM, WB for each instruction in the boxes. Assume that there two levels of bypassing, that the second half of the decode stage performs a read of source registers, and that the first half of the write-back stage writes to the register file. Label all data stalls (Draw an X in the box). Label all data forwards that the forwarding
Ch04.2. Consider the following assembly language code: 10: lw $30, value I1: add $31, $30, $a1 12: add $t1,$t1, Sal 13: lw $t7, ($30) 14: bnez St7, loop 15: add $t1,$t1, $30 16: add $t2, $30, $t4 17: add $t3, $t2, $t5 Consider a pipeline with forwarding, hazard detection, and 1 delay slot for branches. The pipeline is the typical 5-stage IF, ID, EX, MEM, WB MIPS design. For the above code, complete the pipeline diagram below (instructions on the left, cycles on top) for the code. Insert the characters IF, ID, EX, MEM, WB for each instruction in the boxes. Assume that there two levels of bypassing, that the second half of the decode stage performs a read of source registers, and that the first half of the write-back stage writes to the register file. Label all data stalls (Draw an X in the box). Label all data forwards that the forwarding
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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![Ch04.2. Consider the following assembly language code:
10: lw $30, value
I1: add $81, $80, $81
12: add $t1,$t1,$s1
13: lw $t7, ($80)
14: bnez St7, loop
15: add $t1,$t1, $30
16: add $t2, $30, $t4
17: add $t3, $t2, $t5
Consider a pipeline with forwarding, hazard detection, and 1 delay slot for branches. The
pipeline is the typical 5-stage IF, ID, EX, MEM, WB MIPS design. For the above code,
complete the pipeline diagram below (instructions on the left, cycles on top) for the code.
Insert the characters IF, ID, EX, MEM, WB for each instruction in the boxes. Assume that
there two levels of bypassing, that the second half of the decode stage performs a read of
source registers, and that the first half of the write-back stage writes to the register file.
Label all data stalls (Draw an X in the box). Label all data forwards that the forwarding
unit detects (arrow between the stages handing off the data and the stages receiving the
data). What is the final execution time of the code?
lw $80, value
add $s 1,$50,$s 1
add $t1,$t1,$s1
lw $t7, ($50)
bnez $t7, loop
add $t1,$t1,$50
add $t1,$50,$t4
add $t1,$t1,$t5
to
IF
t1
ID
IF
t3 t4 t5
t2
EX MEM WB
ID EX MEM WB
IF
ID
IF
t6
t7 t8 t9 t10 111 112 t13
EX MEM WB
ID EX MEM WB
IF
ID
IF
EX MEM WB
ID EX MEM WB
IF
ID
EX
IF
ID
MEM WB
EX
MEM WB
t14
t15](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F3a2ca6fa-21aa-42fd-b2eb-78f70b7c79d3%2F5ab98378-0bc3-4b4a-8d81-1eafef7d4f15%2F0btm7sx_processed.png&w=3840&q=75)
Transcribed Image Text:Ch04.2. Consider the following assembly language code:
10: lw $30, value
I1: add $81, $80, $81
12: add $t1,$t1,$s1
13: lw $t7, ($80)
14: bnez St7, loop
15: add $t1,$t1, $30
16: add $t2, $30, $t4
17: add $t3, $t2, $t5
Consider a pipeline with forwarding, hazard detection, and 1 delay slot for branches. The
pipeline is the typical 5-stage IF, ID, EX, MEM, WB MIPS design. For the above code,
complete the pipeline diagram below (instructions on the left, cycles on top) for the code.
Insert the characters IF, ID, EX, MEM, WB for each instruction in the boxes. Assume that
there two levels of bypassing, that the second half of the decode stage performs a read of
source registers, and that the first half of the write-back stage writes to the register file.
Label all data stalls (Draw an X in the box). Label all data forwards that the forwarding
unit detects (arrow between the stages handing off the data and the stages receiving the
data). What is the final execution time of the code?
lw $80, value
add $s 1,$50,$s 1
add $t1,$t1,$s1
lw $t7, ($50)
bnez $t7, loop
add $t1,$t1,$50
add $t1,$50,$t4
add $t1,$t1,$t5
to
IF
t1
ID
IF
t3 t4 t5
t2
EX MEM WB
ID EX MEM WB
IF
ID
IF
t6
t7 t8 t9 t10 111 112 t13
EX MEM WB
ID EX MEM WB
IF
ID
IF
EX MEM WB
ID EX MEM WB
IF
ID
EX
IF
ID
MEM WB
EX
MEM WB
t14
t15
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