Convert the C to assembly. y's base address is in $t0. Variable i is in $t4. 1 = 0; while (i <6) ( y[i] = 1 + 5; 1 = 1 + 1; } While: After: addi v $t4 bgt v $t4 add $t5 add v $t5 add v SW < j < addi v > $t5 $t6 St4 V < < < While v F " Szero St1 $t5 $t5 $t5 0( $t5 $t4 V < < > " 7 After v $t5 $t5 $t5 1 > > < Registers 0 5000 6 Szero $t0 St1 $12 $13 $14 $15 $16 4 5 0 0 0 Data memory 0 0 0 0 0 0 0 5000 5004 5008 5012 5016 5020 5024
Convert the C to assembly. y's base address is in $t0. Variable i is in $t4. 1 = 0; while (i <6) ( y[i] = 1 + 5; 1 = 1 + 1; } While: After: addi v $t4 bgt v $t4 add $t5 add v $t5 add v SW < j < addi v > $t5 $t6 St4 V < < < While v F " Szero St1 $t5 $t5 $t5 0( $t5 $t4 V < < > " 7 After v $t5 $t5 $t5 1 > > < Registers 0 5000 6 Szero $t0 St1 $12 $13 $14 $15 $16 4 5 0 0 0 Data memory 0 0 0 0 0 0 0 5000 5004 5008 5012 5016 5020 5024
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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![Convert the C to assembly. y's base address is in $t0. Variable i is in $t4.
1 = 0;
while (i <= 6) {
y[i] = 1 + 5;
i = 1 + 1;
}
addi v
While: bgt V
add
After:
add
add
SW
U.
V
j
<
<
addi v
>
$t4
$t4
$t5
$t5
$t5
$t6
$t4
<
<
>
V While v
F
I
Szero ✓
St1 V
$t5
V
St5 V
$t5 V
0 ( $t5
St4
V
After
$t5
$t5
0
St5
1
V
Registers
0
5000
6
4
5
0
0
0
Szero
$t0
St1
$12
$13
St4
$15
$16
Data memory
0
0
0
5000
5004
5008
5012
5016
5020
5024
0
0
0
0](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F05f3943d-ebc6-4506-9952-39dd520372ca%2F98e64701-9231-445d-8847-b81b5465859c%2Fx2vrvhf_processed.jpeg&w=3840&q=75)
Transcribed Image Text:Convert the C to assembly. y's base address is in $t0. Variable i is in $t4.
1 = 0;
while (i <= 6) {
y[i] = 1 + 5;
i = 1 + 1;
}
addi v
While: bgt V
add
After:
add
add
SW
U.
V
j
<
<
addi v
>
$t4
$t4
$t5
$t5
$t5
$t6
$t4
<
<
>
V While v
F
I
Szero ✓
St1 V
$t5
V
St5 V
$t5 V
0 ( $t5
St4
V
After
$t5
$t5
0
St5
1
V
Registers
0
5000
6
4
5
0
0
0
Szero
$t0
St1
$12
$13
St4
$15
$16
Data memory
0
0
0
5000
5004
5008
5012
5016
5020
5024
0
0
0
0
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