AXY flip-flop has four operations clear to 0, no change, complement and set to 1, when inputs X and Y are 00, 01, 10, and 11, respectively. (a) Tabulate the characteristic table. (b) Derive the characteristic equation (c) Tabulate the excitation table (4) Convert XY Flighlop to JK Fliplop. 0010101 The 'D' inout

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AXY flip-flop has four operations: clear to 0, no change, complement and set to 1, when inputs X and Y are 00, 01, 10, and 11, respectively.
(a) Tabulate the characteristic table.
(b) Derive the characteristic equation
(c) Tabulate the excitation table.
(d) Convert XY Flipflop to JK Flipflop
A4 bit shift register, which shifts one bit to the right at every clock pulse, is initialized to values "1000" for Q0Q1Q2Q3. The 'D' input is
derived from Q0,Q2 and Q3 through two XOR gates as shown in below Fig.
(a) How many clock pulses are needed for pattern 1000 reappears on Q0Q1Q2Q3 and write down logic table?
(b) To what values should the shift register be initialized so that the pattern "1001" occurs after the first clock pulse?
14.9
09
The initial contents of the 4-bit serial-in-parallel-out shift register shown in the figure below is 0110. After 3 clock pulses are applied, the
contents of shift register will be:
Cleck
0
1 1 0
Three JK flipflops are connected as a synchronous counter that goes through the following QcQQA sequence 000-010-011-001-101-
100-111-110-000- Find the connections to the inputs of flipflops and Design the Counter.
Transcribed Image Text:AXY flip-flop has four operations: clear to 0, no change, complement and set to 1, when inputs X and Y are 00, 01, 10, and 11, respectively. (a) Tabulate the characteristic table. (b) Derive the characteristic equation (c) Tabulate the excitation table. (d) Convert XY Flipflop to JK Flipflop A4 bit shift register, which shifts one bit to the right at every clock pulse, is initialized to values "1000" for Q0Q1Q2Q3. The 'D' input is derived from Q0,Q2 and Q3 through two XOR gates as shown in below Fig. (a) How many clock pulses are needed for pattern 1000 reappears on Q0Q1Q2Q3 and write down logic table? (b) To what values should the shift register be initialized so that the pattern "1001" occurs after the first clock pulse? 14.9 09 The initial contents of the 4-bit serial-in-parallel-out shift register shown in the figure below is 0110. After 3 clock pulses are applied, the contents of shift register will be: Cleck 0 1 1 0 Three JK flipflops are connected as a synchronous counter that goes through the following QcQQA sequence 000-010-011-001-101- 100-111-110-000- Find the connections to the inputs of flipflops and Design the Counter.
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