16. The following serial data are applied to the flip-flop through the AND gates as indicated in Figure 7-85. Determine the resulting serial data that appear on the output. There is one clock pulse for each bit time. Assume that 2 is initially 0 and that PRE and CLR are HIGH. Right- most bits are applied first. J: 1010011; 3₂: 0111010; J: 1111000; K₁:0001110; K₂: 1101100; Ky: 1010101 PRE J 2 CLK CLR FIGURE 7-85 K
16. The following serial data are applied to the flip-flop through the AND gates as indicated in Figure 7-85. Determine the resulting serial data that appear on the output. There is one clock pulse for each bit time. Assume that 2 is initially 0 and that PRE and CLR are HIGH. Right- most bits are applied first. J: 1010011; 3₂: 0111010; J: 1111000; K₁:0001110; K₂: 1101100; Ky: 1010101 PRE J 2 CLK CLR FIGURE 7-85 K
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
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Transcribed Image Text:16. The following serial data are applied to the flip-flop through the AND gates as indicated in
Figure 7-85. Determine the resulting serial data that appear on the 2 output. There is one clock
pulse for each bit time. Assume that 2 is initially 0 and that PRE and CLR are HIGH. Right-
most bits are applied first.
J: 1010011; J2: 0111010; J: 1111000; K₁: 0001110; K₂: 1101100;
K: 1010101
PRE
J
2
CLK
CLR
FIGURE 7-85
C
K
D
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