16. The following serial data are applied to the flip-flop through the AND gates as indicated in Figure 7-850. Determine the resulting serial data that appear on the Q output. There is one clock pulse for each bit time. Assume that Q is initially 0 and that and PRE CLR are HIGH. Rightmost bits are applied first. J: 1010011; ₂:01110101111000; K: 0001110; K₂: 1101100; K: 1010101
16. The following serial data are applied to the flip-flop through the AND gates as indicated in Figure 7-850. Determine the resulting serial data that appear on the Q output. There is one clock pulse for each bit time. Assume that Q is initially 0 and that and PRE CLR are HIGH. Rightmost bits are applied first. J: 1010011; ₂:01110101111000; K: 0001110; K₂: 1101100; K: 1010101
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Transcribed Image Text:16. The following serial data are applied to the flip-flop through the AND gates as indicated in Figure 7-85 Ⓒ.
Determine the resulting serial data that appear on the Qoutput. There is one clock pulse for each bit time.
Assume that Q is initially 0 and that
and
PRE
are HIGH. Rightmost bits are applied first.
J₁: 1010011; J₂:0111010; J: 1111000; K: 0001110; K 1101100, K: 1010101
CLK
K₁
CLR
Figure 7-85
C
K
PRE
-Q
CLR
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