4) Design a clocked synchronous state machine with the state/output table shown in the table below, using Rising Edge Triggered (RET) D flip-flops. Use two state variables, Q₁, Qo, with state assignments (S-QiQo) of A-00, B-01, C-11 and D-10. XY ● . . 11 . 11 ● Transition/Output Table QA QB 00 00 00 00 10 10 10 01 01 01 01 10 11 11 State A B D 01 10 11 00 01 10 00 11 00 01 10 11 C C XY QA* QB* Z 00 01 10 11 00 C 01 B A B B Expectations for designing the circuit. Show all work. Use the state variable and state assignments given Develop and provide the transition/output table Develop excitation equations, these are expected to minimized sum of products forms Develop output equation(s), these are expected to minimized sum of products forms Draw the complete logic circuit Next State QB 00 01 11 * = 11 D D D B 00 01 11 10 10 QA* = C D 00 01 11 Z (output) 10 1 0 1 0 00 01 11 10

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Latches and Flip Flop

Just like logic gates, the latches and flip-flops are the important elements of an electronic circuit. The logic gates form the important part of combinatorial circuits, while the latches and flip-flops form the essential part of a sequential circuit. Sequential circuits form the important concept of automata theory in electronics and electrical engineering, these circuits are a kind of logic circuit whose output depends on both present input and past inputs, that is, the input history.