Answer each of the following questions a) Suppose that in 1000 memory references there are 40 misses in L1 cache and 10 misses in L2 cache. If the miss penalty of L2 is 200 clock cycles, hit time of L1 is 1 clock cycle, and hit time of L2 is 15 clock cycles, Find the average memory access time in clock cycles. b) Consider a 32-byte cache with 16 byte blocks, an associativity of 4 and LRU block replacement. The processor has 128KB of physical memory. What is the total number of tag bits in the cache? c) Design a 128KB direct-mapped data cache that uses a 32-bit address and 16 bytes per block. Calculate the following: How many bits are used for the byte offset? Index field? And the tag? d) Three programs are concurrently executing in a multitasking computer with virtual memory pages having 16kB. Each page table entry is 32 bits. What is the minimum numbers of bytes of main memory occupied by the directory pages and page tables for the three programs, if the number of pages per program, in decimal, are as follows: 2445, 3890, and 6342?

Answer each of the following questions a) Suppose that in 1000 memory references there are 40 misses in L1 cache and 10 misses in L2 cache. If the miss penalty of L2 is 200 clock cycles, hit time of L1 is 1 clock cycle, and hit time of L2 is 15 clock cycles, Find the average memory access time in clock cycles. b) Consider a 32-byte cache with 16 byte blocks, an associativity of 4 and LRU block replacement. The processor has 128KB of physical memory. What is the total number of tag bits in the cache? c) Design a 128KB direct-mapped data cache that uses a 32-bit address and 16 bytes per block. Calculate the following: How many bits are used for the byte offset? Index field? And the tag? d) Three programs are concurrently executing in a multitasking computer with virtual memory pages having 16kB. Each page table entry is 32 bits. What is the minimum numbers of bytes of main memory occupied by the directory pages and page tables for the three programs, if the number of pages per program, in decimal, are as follows: 2445, 3890, and 6342?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter6: System Integration And Performance

Section: Chapter Questions

Problem 22VE

See similar textbooks

Similar questions

Answer part d only
CO. A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and the Index ticlds respectively in the addresses generated by the processor?
6. For a direct mapped cache comprising 16 single word blocks answer the following questions. Assume address and word sizes are both 32 bits and that the memory is byte addressed (4 bytes per 32-bit word). Enter answers as numbers only. How many index bits are there? How many offset bits are there? How many tag bits are there?
Given that a 4-way set associative cache memory has 64 KB data and each block contains 32 bytes. The main memory capacity is 4 GB. a. Find the number of bits for the main memory address. ANSWER: b. How many blocks are there in a set? ANSWER: c. How many sets the cache has? ANSWER: d. The main memory address format is => | Tag: bits | blocks sets bits | Set: e. Which set will be mapped by the main memory address 458195h. ANSWER: decimal) bits bits | Word: (in
a) Suppose that in 1000 memory references there are 40 misses in L1 cache and 10 misses in L2 cache. If the miss penalty of L2 is 200 clock cycles, hit time of L1 is 1 clock cycle, and hit time of L2 is 15 clock cycles, Find the average memory access time in clock cycles.
Consider a cache with 32KİB data, 16-word blocks, and 24-bit addresses, answer the following questions: a) For the direct-mapped configuration, determine the number of index bits and tag bits in the 24-bit address. b) For 4-way set associative configuration, determine the number of index bits and tag bits in the 24-bit address. c) For fully associative contiguration, determine the number of index bits and tag bits in the 24-bit address. d) For an 8-way set associative configuration, identify the set number in the cache to which the following 24-bit memory address maps: Ox001Z00 (Hexadecimal notation) where Z is the least significant digit in your student ID (written as a decimal number)
If memory read cycle takes 100 ns and a cache read cycle takes 20 ns, then for four continuous references, the first one brings the main memory contents to cache and the next three from cache. Find the time taken for the Read cycle with and without Cache? What is the Percentage speedup obtained?
3. The table below represents five lines from a cache that uses fully associative mapping with a block size of 8. Identify the address of the shaded data, 0xE6, first in binary and then in hexadecimal. The tag numbers and word id bits are in binary, but the content of the cache (the data) is in hexadecimal. Word id bits Tag 000 001 010 011 100 101 110 111 ------------------------------------------ 1011010 10 65 BA 0F C4 19 6E C3 1100101 21 76 CB 80 D5 2A 7F B5 0011011 32 87 DC 91 E6 3B F0 A6 1100000 43 98 ED A2 F7 4C E1 97 1111100 54 9A FE B3 08 5D D2 88
Suppose a byte-addressable computer using set-associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes.Q.) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
Give me correct solution please.
For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. We assume that each word has 4 bytes. How many words of data are included in one cache line?
For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. a. What is the cache block size in words? b. How many entries does the cache have? Tag 31-13 Index 12-6 Offset 5-0