Answer each of the following questions a) Suppose that in 1000 memory references there are 40 misses in L1 cache and 10 misses in L2 cache. If the miss penalty of L2 is 200 clock cycles, hit time of L1 is 1 clock cycle, and hit time of L2 is 15 clock cycles, Find the average memory access time in clock cycles. b) Consider a 32-byte cache with 16 byte blocks, an associativity of 4 and LRU block replacement. The processor has 128KB of physical memory. What is the total number of tag bits in the cache? c) Design a 128KB direct-mapped data cache that uses a 32-bit address and 16 bytes per block. Calculate the following: How many bits are used for the byte offset? Index field? And the tag? d) Three programs are concurrently executing in a multitasking computer with virtual memory pages having 16kB. Each page table entry is 32 bits. What is the minimum numbers of bytes of main memory occupied by the directory pages and page tables for the three programs, if the number of pages per program, in decimal, are as follows: 2445, 3890, and 6342?

Answer each of the following questions a) Suppose that in 1000 memory references there are 40 misses in L1 cache and 10 misses in L2 cache. If the miss penalty of L2 is 200 clock cycles, hit time of L1 is 1 clock cycle, and hit time of L2 is 15 clock cycles, Find the average memory access time in clock cycles. b) Consider a 32-byte cache with 16 byte blocks, an associativity of 4 and LRU block replacement. The processor has 128KB of physical memory. What is the total number of tag bits in the cache? c) Design a 128KB direct-mapped data cache that uses a 32-bit address and 16 bytes per block. Calculate the following: How many bits are used for the byte offset? Index field? And the tag? d) Three programs are concurrently executing in a multitasking computer with virtual memory pages having 16kB. Each page table entry is 32 bits. What is the minimum numbers of bytes of main memory occupied by the directory pages and page tables for the three programs, if the number of pages per program, in decimal, are as follows: 2445, 3890, and 6342?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Assume a cache of 1 MB organized as 32 bytes each line. The main memory is 256 MB. a. Determine the number of blocks in main memory b. Determine how to split the address (s-r, r, w) for direct mapping. c. Determine how to split the address (s, w) for associative mapping. d. Determine how to split the address (s-d, d, w) for set-associative each cache set is 4 lines of the cache.
QUESTION THREE (4) (a) Explain what is the function of buffer. (b) Give THREE (3) advantages of cache work with the buffer for data transfer. (c) What is "bus-snooping" used for.
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Consider a cache with 32KİB data, 16-word blocks, and 24-bit addresses, answer the following questions: a) For the direct-mapped configuration, determine the number of index bits and tag bits in the 24-bit address. b) For 4-way set associative configuration, determine the number of index bits and tag bits in the 24-bit address. c) For fully associative contiguration, determine the number of index bits and tag bits in the 24-bit address. d) For an 8-way set associative configuration, identify the set number in the cache to which the following 24-bit memory address maps: Ox001Z00 (Hexadecimal notation) where Z is the least significant digit in your student ID (written as a decimal number)
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Consider a cache with 128 blocks. The block size is 32 bytes. Find the number of tag bits, index bits, and offset bits in a 32-bit address if you design it as a) Direct-mapped b) 8-way Set Associative
Consider a 2-block fully associative cache. The following blocks from main memory are accessed which need to be mapped to cache: P, Q, P, R. Which block is replaced from the cache when the last block (block R) is accessed? Assume FIFO replacement policy.
c) The table below represents 5 lines from a 256 line cache that uses direct mapping with a block size of 4 words. Identify the address of the shaded data (F316). Word 10 Line# Tag Word Word 11 Word 00 01 110101 12 34 56 78 010101 54 32 6A D3 000111 29 8C ED F3 001100 33 A2 20 C8 4 110011 9A BC D8 FO
Upload answer sheets Test time left: 02:02:05 Consider a 8-way set associative mapped cache of size 64 MB with block size 8 KB. The size of main memory is 32 GB, Find- i) Number of bits in physical address ii) Number of bits in block-offset i) Number of lines in cache iv) Number of sets in cache v) Tag directory size
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