9. Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of 4. The same processor is upgraded to a pipelined processor with five stages, but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume there are no stalls in the pipeline. What is the speed up achieved in this pipelined processor?

9. Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of 4. The same processor is upgraded to a pipelined processor with five stages, but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume there are no stalls in the pipeline. What is the speed up achieved in this pipelined processor?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Suppose we had a processor design with 5 stages where each stage takes the following amount of time: IF: 400 ps ID: 200 ps EX: 300 ps MEM: 500 ps WB: 200 psQ1: If you choose a pipelined design, what is the CPI? Assume that we have enough instructions such that the brief ramp up period at the beginning and the ramp down period at the end with less than 100% utilization does not matter. Q2: If you choose a pipelined design, what is the average execution time per instruction in picoseconds?
A pipelined processor executing with a constant clock rate has 5 stages. The five stages are Fetch, Decode, Execute, Memory Access and Write Back. Latency of the stages are 100, 80, 120, 150 and 140 nanoseconds respectively. If a register which has a delay of 10 ns is used between the different stages of the pipelined processor. The time taken to execute 2001 instruction for a pipelined processor is microseconds.
We have a 5-stage (IF ID EX MM WB) SPARC CPU (which has delay slots). This CPU has the following characteristics: • The branches are solved at MM stage. • The jumps are solved at EX stage • The base CPI is 1.2 • 25% of the branches are taken • 60% of the delay slots are filled • 10% of the instructions are branches, 20% are jumps What is the overall CPI when control hazards are considered?
Consider a 32-bit processor which supports 70 instructions. Each instruction is 32 bit long and has 4 fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is 8191. How many registers the processor has ?
Given the following latencies-- I-Mem: 200ps, Add: 70ps, Mux: 20ps, ALU: 90ps, Regs: 90ps, D-Mem: 250ps, Sign-Extend: 15ps, Shift-Left-2: 10ps. If the only thing we need to do in a processor is fetch consecutive instructions, what would the cycle time be?
Please help me to do this
A 5-stage pipelined processor has instruction Fetch (IF), Instruction Decode (ID), Operand fetch (OF), perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions? I0: ADD $t2, $t1, $t2 Il: DIV $t4, $t3, $t2 12: MUL $t6, $t5, $t4 Answer:
Microprocessor Question