s. The five sta e, Memory Ac the stages a seconds resp elay of 10 ns i stages of the

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
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A pipelined processor executing with a constant
clock rate has 5 stages. The five stages are
Fetch, Decode, Execute, Memory Access and
Write Back. Latency of the stages are 100, 80,
120, 150 and 140 nanoseconds respectively. If a
register which has a delay of 10 ns is used
between the different stages of the pipelined
processor. The time taken to execute
2001 instruction for a pipelined processor is
microseconds.
Transcribed Image Text:A pipelined processor executing with a constant clock rate has 5 stages. The five stages are Fetch, Decode, Execute, Memory Access and Write Back. Latency of the stages are 100, 80, 120, 150 and 140 nanoseconds respectively. If a register which has a delay of 10 ns is used between the different stages of the pipelined processor. The time taken to execute 2001 instruction for a pipelined processor is microseconds.
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