5.15 Suppose that loads constitute 25% of the typical instruction mix on a cer- tain machine. Suppose further that 15% of these loads miss in the last level of on-chip cache, with a penalty of 120 cycles to reach main memory. What is the contribution of last-level cache misses to the average number of cycles per instruction? You may assume that instruction fetches always hit in the L1 cache. Now suppose that we add an off-chip (L3 or L4) cache that can satisfy 90% of the misses from the last-level on-chip cache, at a penalty of only 30 cycles. What is the effect on cycles per instruction?

5.15 Suppose that loads constitute 25% of the typical instruction mix on a cer- tain machine. Suppose further that 15% of these loads miss in the last level of on-chip cache, with a penalty of 120 cycles to reach main memory. What is the contribution of last-level cache misses to the average number of cycles per instruction? You may assume that instruction fetches always hit in the L1 cache. Now suppose that we add an off-chip (L3 or L4) cache that can satisfy 90% of the misses from the last-level on-chip cache, at a penalty of only 30 cycles. What is the effect on cycles per instruction?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Answer the following questions. A. A computer system has a main memory access time as 60ns. you as a computer organization expert has been asked to reduce the memory access time to 20ns by adding a suitable cache. Assume that the miss probability is 10%. What should be the fastness of cache (in terms of access time) for this requirement? B. Consider the instruction ADD R1, X, which adds the contents of location X from the contents of register R1, and places the result in R1. Show the micro-operations used during fetch and execution phase of the instruction.
On the Motorola 68020 microprocessor, a cache access takes two clock cycles. Data access from main memory over the bus to the processor takes three clock cycles in the case of no wait state insertion; the data are delivered to the processor in parallel with delivery to the cache. a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a clocking rate of 16.67 MHz. b. Repeat the calculations assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the results?
Multicycle execution is better than single cycle execution since it is: a. Every operation is completely carried out within a single clock cycle b. Break up operation so that each stage is executed in 1 clock cycle and allow skipping of unused stages. c. The maximum clock frequency is determined by the slowest instruction in the instruction set. d. A form of parallelism since more than one instruction is executed by the processor in any given cla
18 What is speculation as it relates to parallelization? It is the set of instructions that issues together in one clock cycle and the packet may be determined statically by the compiler or dynamically by the processor. It is a style of instruction set architecture that launches many operations that are defined to be independent in a single wide instruction, typically with many separate opcode fields. It is the number of clock cycles between a load instruction and an instruction that can use the result of the load without stalling the pipeline. O It is an approach whereby the compiler or processor guesses the outcome of an instruction to remove it as a dependence in executing other instructions.
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A program sees a 4% miss rate on both the Instruction Cache and the Data Cache. Every instruction requires access to the Instruction cache. Only 35% of the instructions require data access from the Data Cache. The miss penalty for either the data or the instruction cache is 100 cycles. Assume the average Clocks per Instruction (CPI) is 2 without any memory stalls (this is a hypothetical machine where if there were no misses on that instruction, it would get executed in 2 clock cycles. We are not worrying about how it is implemented, just, that suppose it was possible). Assume the number of instructions in a program is X. F3: What is the total run time of the program including the missed cycles dues to data and instruction misses? F4: What is the ratio of the actual run time (from question F3 above) to the fictitious run time if there were no cache misses at all?
A program sees a 4% miss rate on both the Instruction Cache and the Data Cache. Every instruction requires access to the Instruction cache. Only 35% of the instructions require data access from the Data Cache. The miss penalty for either the data or the instruction cache is 100 cycles. Assume the average Clocks per Instruction (CPI) is 2 without any memory stalls (this is a hypothetical machine where if there were no misses on that instruction, it would get executed in 2 clock cycles. We are not worrying about how it is implemented, just, that suppose it was possible). Assume the number of instructions in a program is X. F1: What is the number of 'instruction miss cycles'? (The number of clock cycles lost due to a miss on the Instruction Cache) F2: What is the number of 'data miss cycles'? F3: What is the total run time of the program including the missed cycles dues to data and instruction misses? F4: What is the ratio of the actual run time (from question F3 above) to the…
A program sees a 4% miss rate on both the Instruction Cache and the Data Cache. Every instruction requires access to the Instruction cache. Only 35% of the instructions require data access from the Data Cache. The miss penalty for either the data or the instruction cache is 100 cycles. Assume the average Clocks per Instruction (CPI) is 2 without any memory stalls (this is a hypothetical machine where if there were no misses on that instruction, it would get executed in 2 clock cycles. We are not worrying about how it is implemented, just, that suppose it was possible). Assume the number of instructions in a program is X. F1: What is the number of 'instruction miss cycles'? (The number of clock cycles lost due to a miss on the Instruction Cache) F2: What is the number of 'data miss cycles'? F3: What is the total run time of the program including the missed cycles dues to data and instruction misses?
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