5.15 Suppose that loads constitute 25% of the typical instruction mix on a cer- tain machine. Suppose further that 15% of these loads miss in the last level of on-chip cache, with a penalty of 120 cycles to reach main memory. What is the contribution of last-level cache misses to the average number of cycles per instruction? You may assume that instruction fetches always hit in the L1 cache. Now suppose that we add an off-chip (L3 or L4) cache that can satisfy 90% of the misses from the last-level on-chip cache, at a penalty of only 30 cycles. What is the effect on cycles per instruction?

5.15 Suppose that loads constitute 25% of the typical instruction mix on a cer- tain machine. Suppose further that 15% of these loads miss in the last level of on-chip cache, with a penalty of 120 cycles to reach main memory. What is the contribution of last-level cache misses to the average number of cycles per instruction? You may assume that instruction fetches always hit in the L1 cache. Now suppose that we add an off-chip (L3 or L4) cache that can satisfy 90% of the misses from the last-level on-chip cache, at a penalty of only 30 cycles. What is the effect on cycles per instruction?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

Asap
Consider the following scenario: we have a byte-addressable computer that employs 2-way set associative mapping and has 16-bit main memory addresses and 32 blocks of cache memory available. Determine the size of the offset field based on the fact that each block includes 8 bytes, and then display your work.
i need the answer quickly
Take into account the following scenario: we have a byte-addressable computer with 2-way set associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. Since there are 8 bytes in a block, you can use that information to calculate how big the offset field has to be.
I need the answer as soon as possible
With drawing Design a machine with a byte addressable main memory of 2¹6 bytes and block size of 8 byte. Assume that an associative mapping cache memory consisting of 32 lines is used with this machin. a- Show the format of cache memory addresser. b- Find tag, and word for the address (0001 0001 0001 1011) using an associative mapping.
Consider a virtual memory system with the following characteristics for accessing memory: 1 nanosecond for a read operation with a hit in cache 5 nanoseconds for a read operation with a miss in cache 2 nanoseconds for a write operation with a hit in cache 10 nanoseconds for a write operation with a miss in cache The cache hit ratio is 0.9 If a sequence of instructions were executed: 100 instruction fetch operations, 60 memory operand read operations, and 40 memory operand write operations, what would be the average memory access time (in nanoseconds) in executing the sequence of instructions:
Consider a computer with the following characteristics: total of 4 Mbyte of main memory; word size of 1 byte; block size of 8 bytes; and cache size of 32 Kbytes. For the main memory address of 3BBCAE, give the corresponding tag and offset value for a fully-associative cache in HEX. You have to show your solution steps.
Answer part d only
Assume miss rate of an instruction cache is 2% and miss rate of data cache IS 4%, If a processor have CPI of 2 without any memory stalls and miss penalty is 100 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed. Assume frequency of all loads and stores is 36%.
Q4 consider a computer with the following characteristics: total of 4 MB of a byte-addressable- main memory; block size of 64 bytes; and cache size of 256 kB. O a. For the main memory addresses of D0005, 512C7, and 7BAAA, give the O corresponding tag, cache line address, and word offsets for a direct-mapped cache. b. Give any two main memory addresses with different tags that map to the same cache slot for a direct-mapped cache.
Take into account the following scenario: we have a byte-addressable computer with 2-way set associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. Since there are 8 bytes in a block, you can use that information to calculate how big the offset field has to be.