4.15 The importance of having a good branch predictor depends on how oftenconditional branches are executed. Together with branch predictor accuracy, thiswill determine how much time is spent stalling due to mispredicted branches. Inthis exercise, assume that the breakdown of dynamic instructions into variousinstruction categories is as follows:R-TypeBEQJMPLWSW40%25%5%25%5%Also, assume the following branch predictor accuracies:Always-TakenAlways-Not-Taken2-Bit45%55%85%4.15.1 [10] <$4.8> Stall cycles due to mispredicted branches increase theCPI. What is the extra CPI due to mispredicted branches with the always-takenpredictor? Assume that branch outcomes are determined in the EX stage, that thereare no data hazards, and that no delay slots are used.

Calculating Extra CPI: From the above information, the first three execution cycles are IF, ID, EX.…

Answered: 4.15 The importance of having a good…

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Instruction class Frequency% 50 % CPI of MI CPI of M2 30 % 20% 3 4. 4. 2. Determine the average CPI for each MI and M2 b. Which machine is faster? And by how much? c. Calculate MIPS rating for MI and M2? d. Assume M1 has 8 core's CPU. The programmers reprogram p such that 90% of its source codes are fully parallelized. Determine the speedup gained when compared with the sequential version of p? Finally, determine the efficiency?
1.a) Explain "Pipeline Scheduling" and "Dynamic Scheduling".1.b)Explain "Static branch prediction" and "dynamic branch prediction".1.c) Explain "Register Renaming".1.d) Explain the "Tomasulo Algorithm".
1A. Consider the following code: AREA ASCENDING, CODE, READONLY ENTRY MOV R8, #2 LOOPO LDR R1, [R2], #4 STR R1, [R3], #4 SUBS R8, R8, #1 CMP R8, #0 BNE LOOPO How many clock cycles are required to complete the execution of the above code on non- pipelined processor assuming each instruction will take 1 cycle to execute completely? Show calculations. How many clock cycles required to complete the execution of the above code on 3-staged pipelined processor? Draw the pipeline diagram for the same. Let one stage requires one clock cycle and assume all memory references hit in cache.
Question 1 A- If you note that the total size of memory is 256G what is the size of address bus if you note that the block size is Qword? B - What is the clock cycle time for processor has 4 GHZ clock rate Question 2 Given a magnetic disk with the following properties Rotation speed = 1000 RPS Average seek = 9 ms, Sector = 256 bytes, Track = 230 sectors Calculate Time of one rotation (in milliseconds) Average time to access a block of 115 consecutive sector Question 3 A- Determine the addressing mode for each of the following instruction Mov Dx,Ax Mov Cl, [100] Mov [Bx], Al Mov Cl , 50 B - Determine the content of Bx, Ax after the execution of the following instruction Mov Bx,1234 h Mov Cx,5678 h Mov Bh.Cl Mov Ch,00h Question 4 A - Find the error for the following instruction if there is any error (2) Mov Ch,DI Mov Bx, Ah Mov Ax, 255 Mov Dh, 1000 Mov Fx,Ax
L
10. 10. Amdahl's Law is as applicable to software as it is to hardware. An oft-cited programming truism states that a program spends 90% of its time executing 10% of its code. Thus, tuning a small amount of program code can often have an enormous effect on the overall performance of a software product. Determine the overall system speedup if: 1. a) 90% of a program is made to run 10 times as fast (900% faster). 2. b) 80% of a program is made to run 20% faster.
3 C language into LC-3 Assembly Language
Write an optimal code that decrements the 32-bit signed value in DO by one if it is odd 02 01 Write a code segment that multiplies the 32-bit unsigned integer in DO by 247. Write a code that negates the signed 32-bit number in DO, assuming that the instruction set does not have negate
Q1 [8]. Translate this following C code into MIPS instructions. Your translation should be direct, without rearranging instructions to achieve better performance. for(i=0; il=j; i+=2) b[i]=a[i]+ a[i+1]; Assume that variables are kept in registers as follows, and that all registers except those indicated as Free are used to keep various variables, so they cannot be used for anything else. i b C Free R7 R2 R3 j R8 a R1 RO,R10,R11,R12
Please answer this question and provide the explanation Assume the values of %ecx is 0x00000005 and %edx is 0x00000003. What would be the value of %ecx and %edx after performing the following instruction? 0x5555555461a <+0>: leal (%ecx, %edx, 8), %edx %ecx = 0x00000005, %edx = 0x0000003A %ecx = 0x00000005, %edx = 0x00000018 %ecx = 0x00000005, %edx = 0x00000030 %ecx = 0x00000005, %edx = 0x00000003 %ecx = 0x00000005, %edx = 0x0000001D %ecx = 0x00000005, %edx = 0x00000040 %ecx = 0x00000055, %edx = 0x0000001D %ecx = 0x00000005, %edx = 0x0000002A %ecx = 0x00000005, %edx = 0x00000025 %ecx = 0x00000005, %edx = 0x00000035
E In the following code block(Reference:Q11), you will a set of assembly instructions with corresponding line numbers (line numbers are for informational purpose only and they are not part of the source code). 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 mov edx, 5 dec ecx jmp LABEL1 mov eax, 1 LABEL1: mul edx jmp ecx mov edx, 0678h sub edx, eax jmp DWORD PTR [edx] neg ebx add ecx, ebx mov eax, 0 For each of the conditions/scenario listed below, indicate the corresponding line number (that cause or is associated with the condition/scenario). Enter 0 (Zero) if the condition is not caused by the block of code. 1) Memory indirect jump: type your answer... type your answer... type your answer... type your answer... 2) Register indirect jump: 3) Relative short jump: type your answer... 5) Two's complement type your answer... 4) Relative near jump: 6) Unreachable code

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