(2) If we want to design a 8-bit Up-Down counter which can counter from 0 to 255. This counter can increase countering when the control signal of Up-Down is high, and decrease countering when Up-Down is low. Now please fill the blanks to complete the design based on the Verilog code in Fig 2(a).
(2) If we want to design a 8-bit Up-Down counter which can counter from 0 to 255. This counter can increase countering when the control signal of Up-Down is high, and decrease countering when Up-Down is low. Now please fill the blanks to complete the design based on the Verilog code in Fig 2(a).
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Question
![2. Design of a 4-bit excess-3 counter and 8-bit Up-Down counter.
(1) Fig 2 shows the logic symbol of an universal 4-bit counter, its truth table and Verilog code. Nov
please design the Verilog code of a 4-bit excess-3 counter (counter from 3 to 12) based on the cod
in Fig 2(a). Please fill the blanks to complete the design.
CLOCK
CNTR4U
CLK
CLR
LD
ENP
11
ENT
DO
D1
D2
D3
778588
88888
QO
Q1
-Q2
-Q3
RCO
CLR
1
0
0
0
0
0
0
0
0
Inputs
LD ENT ENP
1
0
0
0
0
X
0
X
X 0
1
X
X
1
1 1
0
1
0
1
0 1
1
1
1
Current State
Q3 Q2 Q1 QO
Fig 2
X
X
X
X X
X
X X
0
0
0
0 0 0
1 1
1
X
module Vrcntr4u( CLK, CLR, LD, ENP, ENT, D, Q, RCO );
input CLK, CLR, LD, ENP, ENT;
input [3:0] D;
output reg [3:0] Q;
output reg RCO;
0
1
1
1
0
1 1 1 1
X
Q <= 4'd0;
Q <= D;
X
0
1
always (posedge CLK) // Create the counter f-f behavior
if (CLR == 1)
else if (LD == 1)
else if ((ENT-1) && (ENP-1)) Q <- Q + 1;
else
Q <= Q;
Q3*
0
D3
Q3
Q3
always (Q or ENT)
// Create RCO combinational output
if ((ENT == 1) && (Q == 4'd15))
else
RCD = 1;
RCD = 0;
endmodule
0
0
1
0
Next State
Q2* Q1 QO
0
0
0
D2
D1
DO
Q2
Q1
Q2
Q1
0
1
0
0
1
1
0
-10
888
QO
1
0
0
1
0](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F655e5d67-ab19-404c-b883-3aa3c693f6a1%2F9a4e6ea2-5c62-415e-9140-49144ab792f9%2Fqddewf9_processed.png&w=3840&q=75)
Transcribed Image Text:2. Design of a 4-bit excess-3 counter and 8-bit Up-Down counter.
(1) Fig 2 shows the logic symbol of an universal 4-bit counter, its truth table and Verilog code. Nov
please design the Verilog code of a 4-bit excess-3 counter (counter from 3 to 12) based on the cod
in Fig 2(a). Please fill the blanks to complete the design.
CLOCK
CNTR4U
CLK
CLR
LD
ENP
11
ENT
DO
D1
D2
D3
778588
88888
QO
Q1
-Q2
-Q3
RCO
CLR
1
0
0
0
0
0
0
0
0
Inputs
LD ENT ENP
1
0
0
0
0
X
0
X
X 0
1
X
X
1
1 1
0
1
0
1
0 1
1
1
1
Current State
Q3 Q2 Q1 QO
Fig 2
X
X
X
X X
X
X X
0
0
0
0 0 0
1 1
1
X
module Vrcntr4u( CLK, CLR, LD, ENP, ENT, D, Q, RCO );
input CLK, CLR, LD, ENP, ENT;
input [3:0] D;
output reg [3:0] Q;
output reg RCO;
0
1
1
1
0
1 1 1 1
X
Q <= 4'd0;
Q <= D;
X
0
1
always (posedge CLK) // Create the counter f-f behavior
if (CLR == 1)
else if (LD == 1)
else if ((ENT-1) && (ENP-1)) Q <- Q + 1;
else
Q <= Q;
Q3*
0
D3
Q3
Q3
always (Q or ENT)
// Create RCO combinational output
if ((ENT == 1) && (Q == 4'd15))
else
RCD = 1;
RCD = 0;
endmodule
0
0
1
0
Next State
Q2* Q1 QO
0
0
0
D2
D1
DO
Q2
Q1
Q2
Q1
0
1
0
0
1
1
0
-10
888
QO
1
0
0
1
0
![module Vrexcess3 (CLK, CLR, LD, ENP, ENT, D, Q, RCO);
input CLK, CLR, LD, ENP, ENT;
input [3:0] D;
output reg [3:0] Q:
output reg RCO;
always @ (posedge CLK)
if (CLR-1)
else if( LD-1).
else if (ENT && ENP && (
else if (ENT && ENP)
else Q<-Q;
always @(Q or ENT)
if (ENT && (
else
endmodule
(2) If we want to design a 8-bit Up-Down counter which can counter from 0 to 255. This counter
can increase countering when the control signal of Up-Down is high, and decrease countering when
Up-Down is low. Now please fill the blanks to complete the design based on the Verilog code in
Fig 2(a).
module VrUpDown_8b (CLK, CLR, LD, ENP, ENT, Up-Down, D, Q, RCO);
input
input
output reg
output reg.
always @ (posedge CLK)
if (CLR=1)
else if( LD == 1)
else if (ENT && ENP && (
else if (ENT && ENP && (
else Q<-Q;
always @(Q or ENT or Up-Down)
if (
else if (
else
endmodule](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F655e5d67-ab19-404c-b883-3aa3c693f6a1%2F9a4e6ea2-5c62-415e-9140-49144ab792f9%2Fgvfm2xm_processed.png&w=3840&q=75)
Transcribed Image Text:module Vrexcess3 (CLK, CLR, LD, ENP, ENT, D, Q, RCO);
input CLK, CLR, LD, ENP, ENT;
input [3:0] D;
output reg [3:0] Q:
output reg RCO;
always @ (posedge CLK)
if (CLR-1)
else if( LD-1).
else if (ENT && ENP && (
else if (ENT && ENP)
else Q<-Q;
always @(Q or ENT)
if (ENT && (
else
endmodule
(2) If we want to design a 8-bit Up-Down counter which can counter from 0 to 255. This counter
can increase countering when the control signal of Up-Down is high, and decrease countering when
Up-Down is low. Now please fill the blanks to complete the design based on the Verilog code in
Fig 2(a).
module VrUpDown_8b (CLK, CLR, LD, ENP, ENT, Up-Down, D, Q, RCO);
input
input
output reg
output reg.
always @ (posedge CLK)
if (CLR=1)
else if( LD == 1)
else if (ENT && ENP && (
else if (ENT && ENP && (
else Q<-Q;
always @(Q or ENT or Up-Down)
if (
else if (
else
endmodule
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