library IEEE; use IEEE.STD LOGIC_1164.ALL; entity EightToOneMultiplexer is Port ( wo : in STD LOGIC; -- input wl : in STD_LOGIC; -- input w2 : in STD_LOGIC: -- input w3 : in STD LOGIC: w4 : in STD LOGIC; w5 : in STD LOGIC; -- input s : in STD_LOGIC_VECTOR (2 DOWNTO 0) : -- inputs that don't connect to an input signal -- input input -- -- 3 select bits are required. 1 : out STD_LOGIC); -- output end EightTooneMultiplexer; architecture Behavioral of EightToOneMultiplexer is begin WITH 3 SELECT f - wo WHEN "000" wl WHEN "O01" w2 WHEN "O10", w3 WHEN "O11", w4 WHEN "100", w5 WHEN "101", "0' WHEN OTHERS; end Behavioral;
library IEEE; use IEEE.STD LOGIC_1164.ALL; entity EightToOneMultiplexer is Port ( wo : in STD LOGIC; -- input wl : in STD_LOGIC; -- input w2 : in STD_LOGIC: -- input w3 : in STD LOGIC: w4 : in STD LOGIC; w5 : in STD LOGIC; -- input s : in STD_LOGIC_VECTOR (2 DOWNTO 0) : -- inputs that don't connect to an input signal -- input input -- -- 3 select bits are required. 1 : out STD_LOGIC); -- output end EightTooneMultiplexer; architecture Behavioral of EightToOneMultiplexer is begin WITH 3 SELECT f - wo WHEN "000" wl WHEN "O01" w2 WHEN "O10", w3 WHEN "O11", w4 WHEN "100", w5 WHEN "101", "0' WHEN OTHERS; end Behavioral;
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Given the VHDL code for the 8-to-1 Multiplexer, please create a Test Bench file.

Transcribed Image Text:1
library IEEE;
2
use IEEE.STD LOGIC 1164.ALL;
entity EightToOneMultiplexer is
Port ( wo : in STD LOGIC; -- input
6.
wl : in STD LOGIC;
input
--
W2 : in
w3 :
input
input
input
7
STD LOGIC;
8
: in
STD LOGIC;
w4 : in
w5 : in STD LOGIC; -- input
s : in STD_LOGIC_VECTOR (2 DOWNTO 0);
STD LOGIC;
--
10
11
inputs that don't connect to an input signal
12
-- 3 select bits are required.
13
f : out STD LOGIC); -- output
14
end EightToOneMultiplexer;
15
16
architecture Behavioral of EightToOneMultiplexer is
17
18
begin
WITH S SELECT
6T
19
20
f <=
wo WHEN "000",
21
wl WHEN "001"
22
w2 WHEN "010"
23
w3 WHEN "011",
24
w4 WHEN "100",
w5 WHEN "101",
'0' WHEN OTHERS;
25
26
27
28
end Behavioral;
29
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