12. A PABX with five trunks supports 200 extensions. Each extension generates three external calls per 8 hour working day. Average call duration is two minutes. If LCR model is assumed, what is the blocking probability? What is the offered load? an
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- draw the curcuit diagram for 4 channel 4 bit multiplexer implemented using 4 channel 1 bit multiplexer. make sure that i need full circuit to save the final multiplexer in the library.Q6: Sectoring is a way to do what? a. Achieve branch circuits. b. Put each phone call in a different time slot. c. Do SS7 look-ahead call placement. d. Partition Voice mail boxes e. It is an ISDN-PRI way of brining in trunks f. Achieve frequency reuse. g. None of the aboveTo implement 8-to-1 line multiplexer using two 4-to-1 line multiplexer(MUX): O a. The third selctor is connected to the enable line of the first and second MUX. O b. Only the enable line of the first MUX must be connected dirictly to the enable for the second MUX. O c. The third selctor is connected to the enable line of the first MUX which is connected through inverter to the enable of the second MUX. O d. All inputs lines for the first mux must be connected to the input lines for the second mux.
- Q1- Draw a grey code 8 QAM constellation Diagram...This question is of electrical engineering from the course analogue to digital converting and the topic is Digital modulation(Quadrature Amplitude Modulation QAM).. Kindly solve it asap2-bit by 2-bit binary multiplier using ROM VHDL codeConstruct the state diagram...
- The required 7-segmrnt decoder should have 3-inputs (which are the bits of the binary number desired to be designed, call them A,B,C), and 7 outputs (the 7 segments of the display unit which are a, b, c, d, e, f & g). 8. gf a b t la Ob d Dp e d8c Dp The 7-segment to be used is of common anode type. Consequently, any segment will be ON if its input is Low, meaning that for displaying 0 the segments inputs (a,b,c,d,e,f.g) should be (0000001), or g will be OFF while all the others are ON. 1- Make a table explaining the inputs and the corresponding outputs for the 6 combinations input (000.101), assuming the other two combinations as don't care. 2- Find the output as a function of the inputs (A,B,C) using K-map to minimize the expressions 3- Show your design using 2-input, and 3-input NAND gates, and inverter.A uniform quantizer, with average quantization power of 67.5 mW, is used in a PCM system. 1) What is the step-size of this quantizer? 2) If the peak value of the quantizer is 12 volts, what is the number of bits of this quantizer? 3) If the quantizer is mid-tread; . Find the level values of the quantizer. • Draw the stair-case characteristics of the quantizer. 4) If an input signal, m(t) = 10 cos(4πt) is applied to the quantizer, what is the resulting SQNR in dB? 5) If the quantizer is replaced with another quantizer with the same peak value, but with two additional bits, what is the resulting change in the SQNR if m(t) is applied to the new quantizer?4. A data signal with bipolar voltage levels is shown below. The decision threshold is 0 volts. The logic levels are +1 volt for logic 1 and -1 volt for logic 0. Noise with the P.D.F. shown corrupts the signal. Find the probability of error at some instant of time on the condition that logic 0 is sent. LOGIC 1 +1 VOLT -2 1/2 دمت ~IN kla THRESHOLD +2 NOISE P.D.F. -I VOLT. LOGIC 0