1. Consider the following description for a NAND2 gate. entity nand 2 is port (il, i2: in std logic; o : out std logic) ; end nand 2; architecture dataflow of nand 2 is begin o <= il nand i2; end dataflow; The entity description is given below for a four input sum-of-products gate (ab + cd). Give the structural description of the architecture using only the nand_2 gates. Draw a schematic showing your logic gate design and label any signals used. entity and or is port (a, b, c, d: in std_logic; Y out std_logic); end;

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