1. 4.1 Consider the combinational circuit shown in Fig. P4.1. (HDL- see Problem 4.49 ) A - T3 В - C - F T2 D- F2 FIGURE P4.1 Description 1. (a)* Derive the Boolean expressions for T 1 through T 4. Evaluate the outputs F 1 and F 2 as a function of the four inputs. 2. (b) List the truth table with 16 binary combinations of the four input variables. Then list the binary values for T 1 through T 4 and outputs F 1 and F 2 in the table. 3. (c) Plot the output Boolean functions obtained in part (b) on maps and show that the simplified Boolean expressions are equivalent to the ones obtained in part (a).

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For the circuit shown in Fig. P4.1 , (a) Write and verify a gate-level HDL model of the circuit.
2. (b) Compare your results with those obtained for Problem 4.1 .

1. 4.1 Consider the combinational circuit shown in Fig. P4.1. (HDL-
see Problem 4.49 )
A -
T3
В -
C -
F
T2
D-
F2
FIGURE P4.1
Description
1. (a)* Derive the Boolean expressions for T 1 through T 4.
Evaluate the outputs F 1 and F 2 as a function of the four inputs.
2. (b) List the truth table with 16 binary combinations of the four
input variables. Then list the binary values for T 1 through T 4
and outputs F 1 and F 2 in the table.
3. (c) Plot the output Boolean functions obtained in part (b) on
maps and show that the simplified Boolean expressions are
equivalent to the ones obtained in part (a).
Transcribed Image Text:1. 4.1 Consider the combinational circuit shown in Fig. P4.1. (HDL- see Problem 4.49 ) A - T3 В - C - F T2 D- F2 FIGURE P4.1 Description 1. (a)* Derive the Boolean expressions for T 1 through T 4. Evaluate the outputs F 1 and F 2 as a function of the four inputs. 2. (b) List the truth table with 16 binary combinations of the four input variables. Then list the binary values for T 1 through T 4 and outputs F 1 and F 2 in the table. 3. (c) Plot the output Boolean functions obtained in part (b) on maps and show that the simplified Boolean expressions are equivalent to the ones obtained in part (a).
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