1. In MOSFET, the potential on the gate controls the carrier concentration in the semiconductor region beneath the gate so that the channel conductivity can be enhanced. True False 2. In triode region, the drain current in the FET exhibits a nearly linear relationship with drain-source voltage as the name “transistor” indicates (i.e., a contraction of transfer resistor). In triode region, the drain current in the FET exhibits a nearly linear relationship with drain-source voltage as the name “transistor” indicates (i.e., a contraction of transfer resistor). True False 3. In saturation region or pinch-off region, the drain current does not depend on drain-source voltage if one ignores the channel length modulation effect. In saturation region or pinch-off region, the drain current does not depend on drain-source voltage if one ignores the channel length modulation effect. True False 4. For a given capacitance and gate size, NMOS logic device has speed advantage over PMOS logic device because electron mobility is faster than hole mobility. For a given capacitance and gate size, NMOS logic device has speed advantage over PMOS logic device because electron mobility is faster than hole mobility. True False 5. A CMOS inverter uses one NMOS and one PMOS transistor so that one of the transistor is in cut-off region no matter input voltage is low or high. A CMOS inverter uses one NMOS and one PMOS transistor so that one of the transistor is in cut-off region no matter input voltage is low or high. True False
1. In MOSFET, the potential on the gate controls the carrier concentration in the semiconductor region beneath the gate so that the channel conductivity can be enhanced.
In triode region, the drain current in the FET exhibits a nearly linear relationship with drain-source voltage as the name “transistor” indicates (i.e., a contraction of transfer resistor).
In triode region, the drain current in the FET exhibits a nearly linear relationship with drain-source voltage as the name “transistor” indicates (i.e., a contraction of transfer resistor).
In saturation region or pinch-off region, the drain current does not depend on drain-source voltage if one ignores the channel length modulation effect.
In saturation region or pinch-off region, the drain current does not depend on drain-source voltage if one ignores the channel length modulation effect.
For a given capacitance and gate size, NMOS logic device has speed advantage over PMOS logic device because electron mobility is faster than hole mobility.
For a given capacitance and gate size, NMOS logic device has speed advantage over PMOS logic device because electron mobility is faster than hole mobility.
A CMOS inverter uses one NMOS and one PMOS transistor so that one of the transistor is in cut-off region no matter input voltage is low or high.
A CMOS inverter uses one NMOS and one PMOS transistor so that one of the transistor is in cut-off region no matter input voltage is low or high.
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