EE306Fall2018FinalBlank

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Nina K. Telang 1 EE306 Introduction to Computing Fall 2018 Final Exam Dr. Nina Telang (TAs: Vignesh Radhakrishnan, Jefferson Lint, Dylan McCoy, Suhas Raja) UT EID: __________________ Printed Name: ______________________ Your signature is your pledge that you have not and will not cheat on this exam, nor help other students to cheat on this exam. Signature: ______________________ Instructions: 1. This is a 180 minute closed book, closed notes exam. 2. No calculators or other electronic devices are allowed. 3. Please refer to the LC-3 ISA sheet, data path, state graph and other reference sheets which have been attached to the exam. 4. Please answer all questions neatly in the space provided. WRITE YOUR FINAL ANSWER IN THE SPACE PROVIDED FOR EACH QUESTION. ONLY THE FINAL ANSWER WILL BE GRADED. NO PARTIAL CREDIT WILL BE GIVEN. 1. Problem # 1 ____________/20 2. Problem # 2 ____________/15 3. Problem # 3 ____________/10 4. Problem # 4 ____________/10 5. Problem # 5 ____________/10 6. Problem # 6 ____________/15 7. Problem # 7 ____________ /10 8. Problem # 8 ____________ /10

Nina K. Telang 2 1. [20 points] Answer the following short questions in the space provided. (i) [2 points] Consider the LC-3 load instruction, LD. During which stages of the instruction cycle of this instruction are MAR and MDR updated. (ii) [2 points] The INT signal for the keyboard is generated using bits 14 and 15 of the KBSR. Say that A = KBSR[15], and B = KBSR[14]. How would you generate the INT signal given only NOT and OR gates? Write the logic expression. (iii) [4 points] Design a 4-to-16 decoder using two 3-to-8 decoders, one NOT gate, and AND gates (any number that you need). (iv) [2 points] Write an LC-3 code snippet that performs the logical OR operation of the contents in R1 and R2, and puts the result in R3.

Nina K. Telang 3 (v) [4 points] Shown below are the contents of registers before and after the LC-3 instruction at location x3210 is executed. Identify the instruction stored at x3210. Write the instruction in hexadecimal . Answers in any other format will not be considered. Before After R0 xFF1D xFF1D R1 x301C x301C R2 x2F11 x2F11 R3 x5321 x5321 R4 x331F x331F R5 x1F22 x1F22 R6 x01FF x01FF R7 x341F x3211 PC x3210 x3220 N 0 0 Z 1 1 P 0 0 (vi) [6 points] A gated D-latch is shown in the figure below. Answer the following short questions: (a) What is the output A if inputs D and WE are both 1? (b) What is the output A if D=0 and WE=1? (c) List the values of S, R that can never occur given this D-latch? Why will these values never occur? A

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Nina K. Telang 4 2. [15 points] Data is stored at LC-3 memory location x3456 in floating point format such that there is 1-bit for the sign, 5-bits for the exponent, and 10-bits for the fraction. A student wants to write a program that will output the data in decimal format (i.e. the screen will display a real number like 17.75 or -0.5). For this question, give all numerical responses in decimal. (i) What are the smallest and largest exponents that can be represented using the given format? Note that “exponents” refers to the power of 2. (ii) Shown below is a code sn ippet of the student’s code. After the execution of these lines of code, R5 should contain the exponent of the normalized binary representation of the number stored in x3456 (e.g. if m[x3456] = 1.11*2 4 , then R5 will contain 4). A description of the subroutine BitShift is given in the comments of the program. ; begin code snippet ; R0 contains bits 14-10 of m[x3456] isolated in place AND R0, R0, R0 AND R1, R1, R1 ; BitShift bit shifts the value in R0 a certain direction ; it shifts the bits the number of times specified by the value in R1 JSR BitShift LD R4, VAL ADD R5, R0, R4 ; end code snippet (a) What direction should BitShift shift the bits of R0 (right or left)? (b) What value should R1 contain before BitShift is called for the program to work as intended? (c) What value should R4 be loaded with in order for R5 to contain the correct value after this program’s execution?

Nina K. Telang 5 (d) In the BitShift subroutine, the student’s code performed the following steps: Step 1 : Saved the values of R0 through R7 in memory Step 2 : Checked to see if R1=0 Step 3 : If not, then divided the number in R0 by 2, decremented R1, and looped back to Step 2. Step 4 : If R1 = 0, then restored the values in R0 through R7, followed by RET. If R0 = 16 and R1 = 2 before the execution of the subroutine, what will the values of R0 and R1 be after the execution? Does this subroutine work as intended?

Nina K. Telang 6 3. [10 points] Dr. Telang has decided to have you all implement another LC-3 instruction that will have the opcode 1101 (currently not used). This instruction will be called BIC and will clear a specified bit of a register. The format is as follows: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 1 DR SR x x x x x x (i) The least significant 6 bits are marked with an “x.” Some of these bits are going to be reserved for the Selection field, which will identify which bit to clear in the SR and stored in the destination register DR. For example, if the Selection field = 12, then bit 12 of the SR will be cleared. What is the minimum number of bits marked wi th an “x” that need to be reserved for this field? (ii) How many memory accesses does this new instruction make? Include all stages of the instruction cycle. (iii) Is it possible for this instruction to change the condition code bits? If so, give an example. (iv) During the Fetch Operands phase, a temporary register, called TR, is loaded with the value that corresponds to the Selection field (e.g. Selection field = 3, TR = x0008). What logical structure can easily produce the value of TR? (v) Write the microinstructions that take place in the Execute and Store Result phase of the instruction cycle. You are allowed to use the following registers: PC, IR, MAR, MDR, SR, DR, and TR.

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Nina K. Telang 7 4. [10 points] An Aggie has tried implementing two new instructions for the new LC-4 machine. PUSH Rn pushes the data in register Rn onto the stack. Similarly, POP Rn pops the data at the top of the stack and loads into register Rn. The instructions are implemented in the following way: PUSH ADD R6, R6, #-1 STR Rn, R6, #0 POP ADD R6, R6, #1 LDR Rn, R6, #0 (i) Is there an error in the code? If so, then how can you fix it? (ii) For the following stack operations (using the PUSH and POP instructions as implemented in the code shown above), trace the contents of registers. If the contents cannot be known with the given information, place a N/A in the box. Other than R6, the registers initially contain R1=0x1111, R2=0x2222, …R7=0x7777. Each column shows the register contents after all previous operations (in previous columns). PUSH R2 PUSH R1 POP R7 POP R4 PUSH R3 PUSH R4 POP R5 PUSH R6 PUSH R1 POP R5 PUSH R2 PUSH R5 PUSH R3 POP R6 POP R1 R1 = 0x1111 R2 = 0x2222 R3 = 0x3333 R4 = 0x4444 R5 = 0x5555 R6 = 0x4000 R7 = 0x7777 R1 = R2 = R3 = R4 = R5 = R6 = R7 = R1 = R2 = R3 = R4 = R5 = R6 = R7 = R1 = R2 = R3 = R4 = R5 = R6 = R7 = R1 = R2 = R3 = R4 = R5 = R6 = R7 =

Nina K. Telang 8 5. [10 points] An LC-3 operating in Interrupt driven I/O mode has the following input devices connected to it: Keyboard: Interrupt Vector x80, Priority Level 4 Mouse: Interrupt Vector x20, Priority Level 3 The Interrupt Enable bits for both these devices are enabled by default. The following program starts at x3000. LD R0, Count Loop ADD R0, R0, #-1 BRp Loop HALT Count .FILL x02 The keyboard and the mouse ISR both have 3 instructions each including RTI. The mouse raises an interrupt during the decode phase of the ADD instruction when R0 = x01 and the keyboard raises an interrupt during the execute phase of ADD instruction when R0 = x01. Your task is to complete the PC trace which captures the values of PC when entering the fetch phase of instruction cycle. Some of them are already filled for you. PC TRACE x3000 x3002 x3002 x3002 x3003

Nina K. Telang 9 6. [15 points] It’s Throwback Thursday !! Back in the Fall of 1985, Dr. Telang, a freshman in IIT, was introduced to the microprocessor Intel 8085 . Knowing about the 8085 was considered swag back then. It has been more than 3 decades now and Dr. Telang would like y’all to take a look at this vintage machine. Investigate the 8085 Microarchitecture/ISA(see attached sheets) and answer the following questions: (i) What is the maximum data width the 8085 ALU can operate? (ii) What is the maximum number of memory locations that can be addressed by 8085? (iii) Flag Register is an 8-bit register in which five-bit positions contain the status of five condition codes which are Zero (Z), Sign (S), Carry (CY), Parity (P) and Auxiliary carry (AC). The flag register format is shown below: b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 S Z x AC x P x CY Sign (S) flag – If the result of an operation is negative, this flag is set (1), otherwise it is reset (0). Zero (Z) flag – Similar to ‘Z’ condition code of LC -3 Carry (CY) flag – If an instruction results in a carry (for addition operation) or borrow (for subtraction or comparison) out of the MSB, then this flag is set, otherwise reset. Auxiliary Carry (AC) flag – If there is a carry/borrow out of bit 3 and into bit 4 resulting from the execution of an arithmetic operation, it is set otherwise reset. Parity (P) flag – This flag is set when the result of an operation contains an even numbe r of 1’s and is reset otherwise. The table shows the status of the bits in the flag register and accumulator after each of the following instructions are executed. Don’t make any assumptions on the initial state of the registers. Your task is to fill in the blanks. Some are already filled for you. Instruction Accumulator (Hexadecimal) S Z C AC P XRA A 0 0 1 MVI B, x70 0 1 0 0 1 MVI C, x0A 0 1 0 0 1 SUB B 0 1 SBB C ADD C 0

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Nina K. Telang 10 (iv) The 8085 has the ability to combine two registers and use them as a register pair . B and C can be considered as one BC register with B in higher order bit position and C in lower order bit position. Similarly, D and E can be combined to DE, and H and L to HL, where D and H are in higher order positions. MVI D, x0 MVI E, x0 MVI B, xAB MVI C, x0 MOV L,B MOV H,C DAD B DCX H INX D What will be the value of the register pairs after the above program is executed? Fill in the table provided. BC = x DE = x HL = x

Nina K. Telang 11 7. [10 points] Design an FSM having one input X and one output Z, such that Z is the 2’s complement of X. The following are some example input sequences with their corresponding output sequences. In each example listed below the LSB is the rightmost bit, and the MSB is the leftmost bit. Note that the LSB will arrive at the machine input first followed by the more significant bits. Example 1: X = 0001, Z = 1111 Example 2: X = 0001001, Z = 1110111 Example 3: X = 1110111, Z = 0001001 (i) Draw the state graph for this finite state machine. (ii) How many storage elements do you need to implement this FSM? (iii) Complete the state table for this FSM. You may not need all the rows. Present State Next State Z X = 0 X = 1 (iv) Write the logic expression for output Z.

Nina K. Telang 12 8. [10 points] A queue is a data structure where elements are removed in the order they are added (like a bus queue). You would like to implement this data structure using 2 stacks, named inbox and outbox . The idea is that inbox is a stack where queue elements enter. To retrieve elements from the queue, you pop elements from stack outbox . When you PUSH a number to inbox , the number gets pushed to the top of inbox . Pushing a number to outbox works in the same way. Similarly, when you POP an element from either inbox or outbox , the element at the top of the stack gets popped. i. The first figure below shows items that have lined up in the queue, with element X first, and element Z last. Write a sequence of pseudo instructions such that the 2 stacks together implements this queue. Note that elements have already entered the queue, and your task is to use the stacks to get them out in the order they entered. The first pseudo instruction has been shown, with the outcome shown in the Inbox stack. X Inbox Outbox ; Write your pseudo instructions below. The first one is written for you. PUSH Inbox X Y Z

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Nina K. Telang 13 ii. The first figure below shows new elements A, B, C (in that order) have entered the queue. . A snapshot of the two stacks shows that the previous elements X, Y, Z have not been processed yet. Write a sequence of pseudo instructions such that the 2 stacks together implements a queue. Inbox Outbox ; Write your pseudo instructions below. X Y Z A B C

Nina K. Telang 14 Intel 8085 Basic Microarchitecture

Nina K. Telang 15 Intel 8085 Instruction Set Intel 8085 is a fully functional chip that was used in some personal computers during the 80’s. Therefore, the ISA is quite complex and for the sake of this exam, we have provided only the information that is required. Instruction Description MVI r, <value> Immediate Addressing Mode The immediate <value> is placed in the register ‘r’. MOV r1,r2 Register Addressing Mode r2  Source Register r1  Destination Register The value of r2 is placed in r1 ADD r Register Addressing Mode A  A + r Accumulator is added with the register ‘r’ and the result is stored back in the Accumulator SUB r Register Addressing Mode A  A - r The register ‘r’ is subtracted from Accumulator and the result is stored back in the Accumulator. SBB r Register Addressing Mode Subtract with Borrow A  A - r - ‘C’ The register ‘r’ and Carry -bit (C) in Flag are subtracted from the Accumulator and the result is stored back in the Accumulator. DCR B Decrement Register ‘B’ B  B – 1 DCX B (Register Pair) Decrement Register ‘BC’ BC  BC – 1 INR D Increment Register ‘D’ D  D + 1 INX D (Register Pair) Increment Register ‘DE’ DE  DE + 1 DAD B (Register Pair) HL  HL + BC Add Register Pair BC with Register pair HL and the sum is stored back in HL. XRA r Register Addressing Mode A  A XOR r Accumulator and the register ‘r’ are XORed and the result is stored back in the Accumulator.

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Nina K. Telang 16

Nina K. Telang 17 Location I/O Register Function xFE00 Keyboard Status Reg (KBSR) Bit [15] is one when keyboard has received a new character. xFE02 Keyboard Data Reg (KBDR) Bits [7:0] contain the last character typed on keyboard. xFE04 Display Status Register (DSR) Bit [15] is one when device ready to display another char on screen. xFE06 Display Data Register (DDR) Character written to bits [7:0] will be displayed on screen. TRAP vector Assembler Name Description of routine x20 GETC read a single character (no echo) x21 OUT output a character to the monitor x22 PUTS write a string to the console x23 IN print prompt to console, read and echo character from keyboard x25 HALT halt the program

Nina K. Telang 18

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Nina K. Telang 19

Nina K. Telang 20 MUX SELCECT SIGNALS NAME INPUTS PCMUX 00: PC+1 01: BUS 10: ADDER DRMUX 00: IR[11:9] 01: R7 10: SP MARMUX 0: ZEXT[IR[7:0]] 1: ADDER ADDR2MUX 00: SEXT[IR[10:0]] 01: SEXT[IR[8:0]] 10: SEXT[IR[5:0]] 11: 0 ADDR1MUX 0: SR1OUT 1: PC INMUX 00: KBDR 01: KBSR 10: DSR 11: MEM

Nina K. Telang 21

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