HW4-verilog_dataflow

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Jan 9, 2024

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ECEN 340 Homework 4 (40 points) Name: ________Morgan Yang_________ 11. Write 110111 2 as a 6-bit unsigned binary number in Verilog format. (1 pt) 6b’110111 2. Write 2A 16 as an 8-bit signed hexadecimal number in Verilog format. (1 pt) 8’sh2A 3. What binary number would Verilog actually interpret 4’b10110111 as? (1 pt) 0111 4. What is the bit number of the MSB in the data bus declared below? (1 pt) Wire [31:0] DATA_BUS; 32 5. What does this Verilog code do? (1 pt) wire [31:0] DATA_BUS; wire [7:0] H_BYTE; assign DATA_BUS [31:28] = H_BYTE [7:4]; This assignment copies those four bits (the eighth bit to the fifth bit) from H_BYTE and puts them in DATA_BUS’s 32 nd to 28 th bits. 6. What does this Verilog code do? (1 pt) wire [31:0] DATA_BUS; wire [7:0] H_BYTE; assign DATA_BUS [0] = H_BYTE [7]; This assignment copies the eighth bit from H_BYTE and puts it in DATA_BUS’s first bit.

Refer to the Verilog code below for questions 7 and 8: module ADD_4 (A, B, C_OUT, SUM); input wire [3:0] A, B; output wire [3:0] SUM; output wire C_OUT; assign {C_OUT, SUM} = (A + B); // module function endmodule 7. Draw a block diagram of the module described by the above Verilog code. (1 pt) 8. What function does this code describe? In other words, what does the module do? Be specific! (1 pt) This code describes a 4-bit adder. A, B, and SUM are all 4-bit wide and {C_OUT, SUM} is five-bit long using {} for concatenation. When A and B are added together, {C_OUT, SUM} gives the answer. C_OUT represents the carry out, which can be 1 or 0. SUM represents the last four-bit results when A and B are added together. 9. If A1 = 4’b1011, B1 = 4’b0001, C1 = 4’b111x, and D1 = 4’b10z0, what is the result of the following Verilog statements: (1 pt each) assign OUT1 = A1 & B1; assign OUT2 = B1 & D1;

assign OUT3 = A1 | B1; assign OUT4 = ~ B1; assign OUT5 = A1 ^ C1; assign OUT6 = B1 | D1; OUT1 = 4’b0001, OUT2 = 4’b0000, OUT3 = 4’b1011, OUT4 = 4’b1110, OUT5 = 4’b010x, OUT6 = 4’b10x1 10. If A1 = 4’b1011, B2 = 4’b0000, C1 = 4’b111x, and D1 = 4’b10z0, what is the result of the following Verilog statements: (1 pt each) assign OUT7 = A1 && B2; assign OUT8 = A1 | | B2; assign OUT9 = A1 && C1; assign OUT10 = ! B2; OUT7 = 1’b0, OUT8 = 1’b1, OUT9 = 1’bx, OUT10 = 1’b1 11. If SIG_IN = 4’b0000, what is the result of the following Verilog statements: (1 pt each) assign OUT11 = ~SIG_IN; assign OUT12 = !SIG_IN; OUT11 = 4’b1111, OUT12 = 4’b0001 12. If A1 = 4’b1011, B1 = 4’b0001, C1 = 4’b111x, and D1 = 4’b10z0, what is the result of the following Verilog statements: (1 pt each) assign OUT13 = A1 < B1; assign OUT14 = A1 > B1; assign OUT15 = A1 >= C1; assign OUT16 = B1 < D1; OUT13 = 1’b0, OUT14 = 1’b1, OUT15 = 1’bx, OUT16 = 1’bx

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13. If A1 = 4’b1011, B1 = 4’b0001, C1 = 4’b111x, D1 = 4’b10z0, and E1 = 4’b111x, what is the result of the following Verilog statements: (1 pt each) assign OUT17 = A1 != B1; assign OUT18 = A1 == C1; assign OUT19 = E1 == C1; assign OUT20 = E1 === C1; assign OUT21 = C1 === D1; OUT17 = 1’b1, OUT18 = 1’bx, OUT19 = 1’ bx, OUT20 = 1’b1, OUT21 = 1’b0 14. // A1 = 4’b1011; B2 = 4’b0000; assign OUT22 = (A1 == 4’b1011) && (B2 == ’b1111); // what will OUT22 be? (1 pt) OUT22 = 1’b0 15. If A2 = 4, B3 = 10, C1 = 4’b111x, D1 = 4’b10z0, and E1 = 4’b111x, what is the result of the following Verilog statements: (1 pt each) assign OUT23 = (B3 – A2); assign OUT24 = C1 + D1; assign OUT25 = B3 / A2; assign OUT26 = D1 + E1; OUT23 = 6, OUT24 = 4’bxxxx, OUT25 = 2, OUT26 = 4’bxxxx 16. If A1 = 4’b1011 and C1 = 4’b111x, what is the result of the following Verilog statements: (1 pt each) assign OUT27 = &A1; assign OUT28 = |A1; assign OUT29 = ^C1; OUT27 = 1’b0, OUT28 = 1’b1, OUT29 = 1’bx

17. Write continuous assignment Verilog code to model this 2:1 MUX: (3 pts) module MUX(x, y, s, m); input x, s, y; output m; wire w1, w2, w3; assign w2 = x & (~s); assign w3 = y & s; assign m = w2 | w3; endmodule