CET4805 Lab 2

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Electrical Engineering

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Jan 9, 2024

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NEW YORK CITY COLLEGE OF TECHNOLOGY The City University of New York FALL, 2021 Component and Subsystem Design II CET 4805 SECTION OL85 Meeting Day: Monday INSTRUCTOR: Prof. H. PECKAN LAB 2: Designing Decoders and Programming with DE10-Lite

Submission Date 10/11/2021 Lab Objective: The objective of this lab is to write a VHDL entity that implements logic functions that represent circuits needed to activate each of the seven segments. Use only simple VHDL assignment statements in your code to specify each logic function using a Boolean expression. Lab Overview: Creating a New Project 1. Open the Quartus software. Select File – New Project Wizard. Enter the appropriate drive letter for the designated storage area on the computer you are using followed by the working directory such as C:\My Documents\CET4805\Lab2. Don’t forget to create the folder Lab2 under the subfolder of your path. Assign the project name Lab2. Creating a VHDL File and Symbol for the Code (bdf) 2. Open a new VHDL Device Design file (File > New) by highlighting VHDL File. Type the VHDL codes shown in Text Box. 3. File name vhdl2_1.vhd must be chosen according to which approach is being used. Save the VHDL file as vhdl2_1.vhd as part of our project under your subfolder. Place a check mark in the space labeled Add file to current project and press Save. DO NOT COMPILE THE FILE AT THIS POINT ! 4. Select File > Create/Update > Create Symbol Files for Current File to create a symbol file for the VHDL code entered. A display window should soon appear stating that the Create Symbol File was (or not) successful. Click OK and close the Compilation Report window. 5. Open a new Schematic file (File > New) by highlighting Block Diagram/Schematic File. And click OK. And construct the circuit shown in Figure 2 using the symbols you just created. Each symbol should be available in the Project Library in the Symbol diagonal box. (Right click on the bdf window and then -> Insert -> Symbol -> Project -> vhdl2_1) To insert pins, right click and then, -> Insert -> Symbol -> c:/intelfpga…/ -> primitives -> pin -> input (or output) To create MULTIPLE pins (a bus) you need to use the following example format on Properties section of the Pins to name the bus. 6. Before compiling this bdf file, we need to name this bdf file and save it as part of our project under your subfolder. Choose File > Save As and enter File name as lab2.bdf. Place a check mark in the space labeled Add file to current project and press Save. 7. Compile the project by selecting Processing > Start Compilation, or press Ctrl-L, or use the Compilation button in the toolbar. The compilation takes several seconds. When it is complete it

should give a message that indicates, “Full compilation was successful”. Press OK. If unsuccessful, correct all errors and try to re-compile. Simulating a Vector Waveform File (University Program vwf) 8. As you have done step in the Part 1, you need to create a Vector Waveform File (vwf) to simulate a design(bdf) file. Add all inputs and output, specify an end time of 20 μs for our waveform display (Edit -> Set End Time) , and then save it as lab2.vwf. 9. When creating the D[3..0] bus, enter D for the bus name, select Hexadecimal for the Radix, and enter 4 for the Bus Width in the Node Properties window. When created, the D waveform will appear with a plus sign implying that it can be ungrouped to show the individual bits, D[3], D[2], D[1], and D[0]. After adding the input vector D and the output vector S, highlight D and go to count Value in the simulation waveform editor toolbar as shown below. In the Count Value window set the Radix to Hexadecimal. The start value must be 0 and increment the values by 1. This will simulate the switch inputs starting at 0000 and increment D by 1 for each clock count giving 0001 the for the next input. For count enter 1 and select us. 10. Run the simulation for your program by clicking on Run Functional Simulation in the toolbar or by going to Simulation > Run Functional simulation. The Simulation Waveform editor will give you the output for S when D = any given input. This is based on what you set it equal to in the code. Lab implementation Source code

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Block diagram Compilation result

Vector waveform / Clock diagrams Vector waveform Simulation for output/after simulation Conclusion and summary: Throughout this lab, I successfully wrote a VHDL entity that implements logic functions that represent circuits needed to activate each of the seven segments. I was also able to only use simple VHDL assignment statements in your code to specify each logic function using a Boolean expression.